Datasheet

216
32133D–11/2011
UC3D
16. External Interrupt Controller (EIC)
Rev: 3.0.2.0
16.1 Features
• Dedicated interrupt request for each interrupt
• Individually maskable interrupts
• Interrupt on rising or falling edge
• Interrupt on high or low level
• Asynchronous interrupts for sleep modes without clock
• Filtering of interrupt lines
• Non-Maskable NMI interrupt
16.2 Overview
The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each
external interrupt has its own interrupt request and can be individually masked. Each external
interrupt can generate an interrupt on rising or falling edge, or high or low level. Every interrupt
input has a configurable filter to remove spikes from the interrupt source. Every interrupt pin can
also be configured to be asynchronous in order to wake up the part from sleep modes where the
CLK_SYNC clock has been disabled.
A Non-Maskable Interrupt (NMI) is also supported. This has the same properties as the other
external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any
other interrupt mode.
The EIC can wake up the part from sleep modes without triggering an interrupt. In this mode,
code execution starts from the instruction following the sleep instruction.
16.3 Block Diagram
Figure 16-1. EIC Block Diagram
Edge/Level
Detector
Mask
IRQn
EXTINTn
NMI
INTn
LEVEL
MODE
EDGE
IER
IDR
ICR
CTRL
ISR
IM R
Filter
FILTER
Polarity
control
LEVEL
MODE
EDGE
Asynchronus
detector
EIC_WAKE
Enable
EN
DIS
CTRL
CLK_SYNC
Wake
detect
ASYNC