Datasheet

210
32133D–11/2011
UC3D
15.6.1 Control Register
Name: CTRL
Access Type: Read/Write
Offset: 0x000
Reset Value: 0x00010080
•KEY
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads
as zero.
• TBAN: Time Ban Prescale Select
Counter bit TBAN is used as watchdog “banned” time frame. In this time frame clearing the WDT timer is forbidden, otherwise a
watchdog reset is generated and the WDT timer is cleared.
• CSSEL: Clock Source Select
0: Select the system RC oscillator (RCSYS) as clock source.
1: Select the 32KHz crystal oscillator (OSC32K) as clock source.
• CEN: Clock Enable
0: The WDT clock is disabled.
1: The WDT clock is enabled.
• PSEL: Time Out Prescale Select
Counter bit PSEL is used as watchdog timeout period.
• FCD: Flash Calibration Done
This bit is set after any reset.
0: The flash calibration will be redone after a watchdog reset.
1: The flash calibration will not be redone after a watchdog reset.
• SFV: WDT Control Register Store Final Value
0: WDT Control Register is not locked.
1: WDT Control Register is locked.
Once locked, the Control Register can not be re-written, only a reset unlocks the SFV bit.
•MODE: WDT Mode
0: The WDT is in basic mode, only PSEL time is used.
1: The WDT is in window mode. Total timeout period is now TBAN+PSEL.
Writing to this bit when the WDT is enabled has no effect.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
- TBAN CSSEL CEN
15 14 13 12 11 10 9 8
- - - PSEL
76543210
FCD - - - SFV MODE DAR EN