Datasheet

207
32133D–11/2011
UC3D
The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT
timeout period
T
timeout
= T
tban
+ T
psel
= (2
(TBAN+1)
+ 2
(PSEL+1)
) / f
clk_cnt
where T
tban
sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR
bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and the
code will start executing form the boot vector, see Figure 15-5 on page 207. The WDT counter
will be cleared.
Writing a one to the CLR.WDTCLR bit within the T
psel
period will clear the WDT counter and the
counter starts counting from zero (t=t
0
), entering T
tban
, see Figure 15-4 on page 207.
If the value in the CTRL Register is changed, the WDT counter will be cleared without a watch-
dog reset, regardless of if the value in the WDT counter and the TBAN value.
If the WDT counter reaches T
timeout
, the counter will be cleared, the device will receive a reset
and the code will start executing form the boot vector.
Figure 15-4. Window Mode WDT Timing Diagram
Figure 15-5. Window Mode WDT Timing Diagram, clearing within T
tban
, resulting in watchdog reset.
T
tban
T
psel
Timeout
Write one to
CLR.WDTCLR
Watchdog reset
t=t
0
T
tban
T
psel
Timeout
Write one to
CLR.WDTCLR
Watchdog reset
t=t
0