Datasheet

206
32133D–11/2011
UC3D
Figure 15-2. Basic Mode WDT Timing Diagram, normal operation.
If the WDT counter is not cleared within T
psel
a watchdog reset will be issued at the end of T
psel
,
see Figure 15-3 on page 206.
Figure 15-3. Basic Mode WDT Timing Diagram, no clear within T
psel
.
15.5.1.6 Watchdog Reset
A watchdog reset will result in a reset and the code will start executing from the boot vector,
please refer to the Power Manager chapter for details. If the Disable After Reset (DAR) bit in the
CTRL Register is zero, the WDT counter will restart counting from zero when the watchdog reset
is released.
If the CTRL.DAR bit is one the WDT will be disabled after a watchdog reset. Only the CTRL.EN
bit will be changed after the watchdog reset. However, if WDTAUTO fuse is configured to enable
the WDT after a watchdog reset, and the CTRL.FCD bit is zero, writing a one to the CTRL.DAR
bit will have no effect.
15.5.2 Window Mode
The window mode can protect against tight loops of runaway code. This is obtained by adding a
ban period to timeout period. During the ban period clearing the WDT counter is not allowed.
If the WDT Mode (MODE) bit in the CTRL Register is one, the WDT is in window mode. Note
that the CTRL.MODE bit can only be changed when the WDT is disabled (CTRL.EN=0).
T
psel
Timeout
Write one to
CLR.WDTCLR
Watchdog reset
t=t
0
T
psel
Timeout
Write one to
CLR.WDTCLR
Watchdog reset
t=t
0