Datasheet

193
32133D–11/2011
UC3D
14.6.8 Wake Enable Register
Name: WER
Access Type: Read/Write
Offset: 0x1C
Reset Value: 0x00000000
When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
This register enables the wakeup signal from the AST.
• PERn: Periodic n
0: The CPU will not wake up from sleep mode when the selected bit in the prescaler has a 0-to-1 transition.
1: The CPU will wake up from sleep mode when the selected bit in the prescaler has a 0-to-1 transition.
• ALARMn: Alarm n
0: The CPU will not wake up from sleep mode when the counter reaches the selected alarm value.
1: The CPU will wake up from sleep mode when the counter reaches the selected alarm value.
• OVF: Overflow
0: A counter overflow will not wake up the CPU from sleep mode.
1: A counter overflow will wake up the CPU from sleep mode.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - PER1 PER0
15 14 13 12 11 10 9 8
- - - - - - ALARM1 ALARM0
76543210
-------OVF