Datasheet

188
32133D–11/2011
UC3D
14.6.3 Status Register
Name: SR
Access Type: Read-only
Offset: 0x08
Reset Value: 0x00000000
• CLKRDY: Clock Ready
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the SR.CLKBUSY bit has a 1-to-0 transition.
• CLKBUSY: Clock Busy
0: The clock is ready and can be changed.
1: CLOCK.CEN has been written and the clock is busy.
• READY: AST Ready
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the SR.BUSY bit has a 1-to-0 transition.
• BUSY: AST Busy
0: The AST accepts writes to CR, CV, SCR, WER, ARn, and PIRn.
1: The AST is busy and will discard writes to CR, CV, SCR, WER, ARn, and PIRn.
• PERn: Periodic n
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the selected bit in the prescaler has a 0-to-1 transition.
• ALARMn: Alarm n
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the counter reaches the selected alarm value.
• OVF: Overflow
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when an overflow has occurred.
31 30 29 28 27 26 25 24
- - CLKRDY CLKBUSY - - READY BUSY
23 22 21 20 19 18 17 16
- - - - - - PER1 PER0
15 14 13 12 11 10 9 8
- - - - - - ALARM1 ALARM0
76543210
-------OVF