Datasheet

183
32133D–11/2011
UC3D
(e.g. 2000). The date is automatically compensated for leap years, assuming every year divisible
by 4 is a leap year.
All interrupts work the same way in calendar mode as in counter mode. However, the Alarm
Register (ARn) must be written in time/date format for the alarm to trigger correctly.
14.5.3 Interrupts
The AST can generate five separate interrupt requests:
• OVF: OVF
• PER: PER0, PER1
• ALARM: ALARM0, ALARM1
• CLKREADY
• READY
This allows the user to allocate separate handlers and priorities to the different interrupt types.
The generation of the PER interrupt is described in Section 14.5.3.1., and the generation of the
ALARM interrupt is described in Section 14.5.3.2. The OVF interrupt is generated when the
counter overflows, or when the alarm value is reached, if the Clear on Alarm bit in the Control
Register is one. The CLKREADY interrupt is generated when SR.CLKBUSY has a 1-to-0 transi-
tion, and indicates that the clock synchronization is completed. The READY interrupt is
generated when SR.BUSY has a 1-to-0 transition, and indicates that the synchronization
described in Section 14.5.5 is completed.
An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared
by writing a one to the corresponding bit in the Status Clear Register (SCR).
The AST interrupts can wake the CPU from any sleep mode where the source clock and the
interrupt controller is active.
14.5.3.1 Periodic interrupt
The AST can generate periodic interrupts. If the PERn bit in the Interrupt Mask Register (IMR) is
one, the AST will generate an interrupt request on the 0-to-1 transition of the selected bit in the
prescaler when the AST is enabled. The bit is selected by the Interval Select field in the corre-
sponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of
where f
CS
is the frequency of the selected clock source.
The corresponding PERn bit in the Status Register (SR) will be set when the selected bit in the
prescaler has a 0-to-1 transition.
f
PA
f
CS
2
INSEL 1+
-------------------------=