Datasheet

181
32133D–11/2011
UC3D
• Peripheral Bus clock (PB clock). This is the clock of the peripheral bus the AST is connected
to.
• Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be
enabled before use, and remains enabled in sleep modes when the PB clock is active.
14.4.3 Interrupts
The AST interrupt request lines are connected to the interrupt controller. Using the AST inter-
rupts requires the interrupt controller to be programmed first.
14.4.4 Debug Operation
The AST prescaler and counter is frozen during debug operation, unless the Run In Debug bit in
the Development Control Register is set and the bit corresponding to the AST is set in the
Peripheral Debug Register (PDBG). Please refer to the On-Chip Debug chapter in the
AVR32UC Technical Reference Manual, and the OCD Module Configuration section, for details.
If the AST is configured in a way that requires it to be periodically serviced by the CPU through
interrupts or similar, improper operation or data loss may result during debugging.
14.5 Functional Description
14.5.1 Initialization
Before enabling the AST, the internal AST clock CLK_AST_PRSC must be enabled, following
the procedure specified in Section 14.5.1.1. The Clock Source Select field in the Clock register
(CLOCK.CSSEL) selects the source for this clock. The Clock Enable bit in the Clock register
(CLOCK.CEN) enables the CLK_AST_PRSC.
When CLK_AST_PRSC is enabled, the AST can be enabled by writing a one to the Enable bit in
the Control Register (CR.EN).
14.5.1.1 Enabling and disabling the AST clock
The Clock Source Selection field (CLOCK.CSSEL) and the Clock Enable bit (CLOCK.CEN) can-
not be changed simultaneously. Special procedures must be followed for enabling and disabling
the CLK_AST_PRSC and for changing the source for this clock.
To enable CLK_AST_PRSC:
• Write the selected value to CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
• Write a one to CLOCK.CEN, without changing CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
To disable the clock:
• Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
14.5.1.2 Changing the source clock
The CLK_AST_PRSC must be disabled before switching to another source clock. The Clock
Busy bit in the Status Register (SR.CLKBUSY) indicates whether the clock is busy or not. This
bit is set when the CEN bit in the CLOCK register is changed, and cleared when the CLOCK reg-
ister can be changed.