Datasheet

166
32133D–11/2011
UC3D
13.6.18 Generic Clock Control
Name: GCCTRL
Access Type: Read/Write
Offset: 0x0060-0x0080
Reset Value: 0x00000000
There is one GCCTRL register per generic clock in the design.
• DIV: Division Factor
• OSCSEL: Generic Clock Source Selection
• DIVEN: Divide Enable
0: The generic clock equals the undivided source clock.
1: The generic clock equals the source clock divided by 2*(DIV+1).
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
DIV
15 14 13 12 11 10 9 8
OSCSEL
76543210
------DIVENCEN
Table 13-9. Generic Clock Sources
OSCSEL Clock Description
0 RCSYS System RC oscillator clock
1 32 KHz clock Output clock from OSC32
2 OSC0 out Output clock from Oscillator 0
3 PLL0 out Output from PLL 0
4 PLL1 out Output from PLL 1
5 CPU clock The clock the CPU runs on
6 HSB clock High Speed Bus clock
7 PBA clock Peripheral Bus A clock
8 PBB clock Peripheral Bus B clock
9 RC120M
Output clock from Oscillator
120Mhz
10-15 Reserved