Datasheet

153

32133D–11/2011

UC3D

• PLLOSC: PLL Oscillator Select

0: Oscillator 0 is the source for the PLL.

others: Reserved.

• PLLEN: PLL Enable

0: PLL is disabled.

1: PLL is enabled.

Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please

refer to the UNLOCK register description for details.

Table 13-4. PLLOPT Fields Description

Description

PLLOPT[0]: VCO frequency

080MHz<f

vco

<180MHz

1 160MHz<f

vco

<240MHz

PLLOPT[1]: Output divider

PLL

= f

vco

PLL

= f

vco

PLLOPT[2]

0 Wide Bandwidth Mode enabled

1 Wide Bandwidth Mode disabled