Datasheet

152
32133D–11/2011
UC3D
13.6.8 PLL Control Register
Name: PLL0,1
Access Type: Read/Write
Offset: 0x001C-0x0020
Reset Value: 0x00000000
•
PLLCOUNT: PLL Count
Specifies the number of slow clock cycles before ISR:LOCKn will be set after PLLn has been written, or after PLLn has been
automatically re-enabled after exiting a sleep mode.
• PLLMUL: PLL Multiply Factor
• PLLDIV: PLL Division Factor
These field determine the ratio of the PLL output frequency (voltage controlled oscillator frequency f
VCO
) to the source oscillator
frequency:
f
VCO
= (PLLMUL+1)/(PLLDIV) • f
OSC
if PLLDIV > 0.
f
VCO
= 2*(PLLMUL+1) • f
OSC
if PLLDIV = 0.
If PLLOPT[1] field is set to 0:
f
PLL
= f
VCO.
If PLLOPT[1] field is set to 1:
f
PLL
= f
VCO
/ 2
.
Note that the MUL field cannot be equal to 0 or 1, or the behavior of the PLL will be undefined.
PLLDIV gives also the input frequency of the PLL (f
IN):
if the PLLDIV field is set to 0: fIN= fOSC
if the PLLDIV field is greater than 0: fIN= fOSC / (2 * PLLDIV)
• PLLOPT: PLL Option
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range.
PLLOPT[1]: Enable the extra output divider.
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time).
31 30 29 28 27 26 25 24
- - PLLCOUNT
23 22 21 20 19 18 17 16
---- PLLMUL
15 14 13 12 11 10 9 8
---- PLLDIV
76543210
- - PLLOPT PLLOSC PLLEN