Datasheet

15
32133D–11/2011
UC3D
independently for each I/O line through the GPIO Controller. After reset, I/O lines default as
inputs with pull-up resistors disabled.
4.1.5 High drive pins
Four I/O lines can be used to drive twice current than other I/O capability (see Electrical
Characteristics section).
4.2 Power Considerations
4.2.1 Power Supplies
The UC3D has several types of power supply pins:
• VDDIO: Powers Digital I/O lines. Voltage is 3.3V nominal.
• VDDIN: Powers the internal regulator. Voltage is 3.3V nominal.
• VDDCORE : Powers the internal core digital logic. Voltage is 1.8 V nominal.
• VDDANA: Powers the ADC and Analog I/O lines. Voltage is 3.3V nominal.
The ground pins GND is dedicated to VDDIO and VDDCORE. The ground pin for VDDANA is
GNDANA.
Refer to ”Electrical Characteristics” on page 716 for power consumption on the various supply
pins.
4.2.2 Voltage Regulator
The UC3D embeds a voltage regulator that converts from 3.3V nominal to 1.8V with a load of up
to 100 mA. The regulator is intended to supply the logic, memories, oscillators and PLLs. See
Section 4.2.3 for regulator connection figures.
Adequate output supply decoupling is mandatory on VDDOUT to reduce ripple and avoid oscil-
lations. The best way to achieve this is to use two capacitors in parallell between VDDOUT and
GND as close to the chip as possible. Please refer to Section 32.9.1 for decoupling capacitors
values and regulator characteristics. VDDOUT can be connected externally to the 1.8V domains
to power external components.
48-pin Package 64-pin Package Pin Name
32 44 PA20
33 45 PA21
34 46 PA22
35 47 PA23