Datasheet

143
32133D–11/2011
UC3D
Although it is not recommended to override default factory settings, it is still possible to override
these default values by writing to those registers. To prevent unexpected writes due to software
bugs, write access to this register is protected by a locking mechanism, for details please refer to
the UNLOCK register description.
13.5.8 System RC Oscillator (RCSYS)
The system RC oscillator (RCSYS) has a 3 cycles startup time, and is always available except in
Static mode. The system RC oscillator operates at a nominal frequency of 115 kHz, and is cali-
brated using the RCCR.CALIB Calibration field. After a Power On Reset, the RCCR.CALIB field
is loaded with a factory defined value stored in the Flash fuses.
Although it is not recommended to override default factory settings, it is still possible to override
these default values by writing to the RCCR.CALIB field. To prevent unexpected writes due to
software bugs, write access to this register is protected by a locking mechanism, for details
please refer to the UNLOCK register description.
13.5.9 120MHz RC Oscillator (RC120M)
The 120MHz RC Oscillator can be used for the main clock in the device, as described in the
Power Manager chapter. The oscillator can be used as source for the generic clocks, as
described in ”Generic clocks” on page 140. To enable the clock, the user must write a one to the
EN bit in the RC120MCR register, and read back the RC120MCR register until the EN bit reads
one. The clock is disabled by writing zero to the EN bit.
The oscillator is automatically switched off in certain sleep modes to reduce power consumption,
as described in the Power Manager chapter.
13.5.10 General Purpose Low Power Registers
The GPLP registers are 32-bit registers that are reset only by power-on-reset. User soft-
ware can
use these registers to save context variables in a very low power mode.
13.5.11 Interrupts
The SCIF has 8 separate interrupt sources. Refer to the PCLKSR register description.
The interrupt sources will generate a interrupt request if the corresponding bit in the Interrupt
Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the
Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the
Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit
in the Interrupt Status Register (ISR) is cleared by writing a one to the corresponding bit in the
Interrupt Clear Register (ICR).