Datasheet

141
32133D–11/2011
UC3D
Figure 13-3. Generic clock generation
13.5.4.1 Enabling a generic clock
A generic clock is enabled by writing the CEN bit in GCCTRL to one. Each generic clock can
individually select a clock source by setting the OSCSEL bits. The source clock can optionally be
divided by writing DIVEN to one and the division factor to DIV, resulting in the output frequency:
f
GCLK
= f
SRC
/ (2*(DIV+1))
13.5.4.2 Disabling a generic clock
The generic clock can be disabled by writing CEN to zero or entering a sleep mode that disables
the PB clocks. In either case, the generic clock will be switched off on the first falling edge after
the disabling event, to ensure that no glitches occur. If CEN is written to zero, the bit will still read
as one until the next falling edge occurs, and the clock is actually switched off. When writing
CEN to zero, the other bits in GCCTRL should not be changed until CEN reads as zero, to avoid
glitches on the generic clock.
When the clock is disabled, both the prescaler and output are reset.
13.5.4.3 Changing clock frequency
When changing generic clock frequency by writing GCCTRL, the clock should be switched off by
the procedure above, before being re-enabled with the new clock source or division setting. This
prevents glitches during the transition.
13.5.4.4 Generic clock implementation
In UC3D, there are nine generic clocks. These are allocated to different functions as shown in
Table 13-2. Note that only GCLK2-0 are routed out.
Divider
OSCSEL
Generic Clock
DIV
0
1
DIVEN
Mask
CEN
Sleep Controller
Table 13-2. Generic clock allocation
Clock number Function
0 GCLK0, GLOC
1GCLK1
2GCLK2