Datasheet

14
32133D–11/2011
UC3D
4.1 I/O Line Considerations
4.1.1 JTAG Pins
The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI
pins have pull-up resistors when JTAG is enabled. TDO pin is an output, driven at VDDIO, and
has no pull-up resistor. These JTAG pins can be used as GPIO pins and muxed with peripherals
when the JTAG is disabled.
4.1.2 RESET_N Pin
The RESET_N pin is a schmitt input and integrates a programmable pull-up resistor to VDDIO.
As the product integrates a power-on reset detector, the RESET_N pin can be left unconnected
in case no reset from the system needs to be applied to the product.
The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debug-
ging, it must not be driven by the application.
4.1.3 TWI Pins
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with inputs with spike-filtering. When used as GPIO pins or used for other peripherals, the
pins have the same characteristics as GPIO pins.
4.1.4 GPIO Pins
All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed
EXTTRIG ADCIFD EXTTRIG Input
AD7 - AD0 ADC Inputs Analog
Power
VDDIO Digital I/O Power Supply
Power
Input
3.0 V to 3.6V.
VDDANA Analog Power Supply
Power
Input
3.0 V to 3.6V
ADVREF Analog Reference Voltage
Power
Input
2.6 V to 3.6 V
VDDCORE Core Power Supply
Power
Input
1.65 V to 1.95 V
VDDIN Voltage Regulator Input
Power
Input
3.0 V to 3.6V
VDDOUT Voltage Regulator Output
Power
Output
1.65 V to 1.95V
GNDANA Analog Ground Ground
GND Ground Ground
General Purpose I/O pin - GPIOA, GPIOB
PA31 - PA00 General Purpose I/O Controller GPIO A I/O
PB18 - PB00 General Purpose I/O Controller GPIO B I/O
Table 4-1. Signal Descriptions List