Datasheet

136
32133D–11/2011
UC3D
12.8 Module Configuration
The specific configuration for each PM instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks. Please refer to the “Synchronous
Clocks”, “Peripheral Clock Masking” and “Sleep Modes” sections for details.
Table 12-8. Power Manager Clock Name
Module Name Clock Name
PM CLK_PM
Table 12-9. Register Reset Values
Register Reset Value
VERSION 0x00000412
Table 12-10. Effect of the Different Reset Events
Power-On
Reset
External
Reset
Watchdog
Reset
BOD
Reset
CPU Error
Reset
OCD
Reset
JTAG
Reset
CPU/HSB/PBx
(excluding Power Manager)
Y Y YYYYY
32KHz oscillator Y N NNNNN
AST control register Y N NNNNN
Watchdog control register Y Y N Y Y Y Y
Voltage Calibration register
Y N NNNNN
RC Oscillator Calibration register Y N NNNNN
BOD control register Y Y Y N Y Y Y
Bandgap control register Y Y Y N Y Y Y
Clock control registers Y Y YYYYY
OSC control registers Y Y YYYYY
OCD system and OCD registers Y Y N Y Y N Y