Datasheet

119
32133D–11/2011
UC3D
12.7.5 Clock Mask
Name: CPUMASK/HSBMASK/PBAMASK/PBBMASK
Access Type: Read/Write
Offset: 0x020-0x02C
Reset Value: -
• MASK: Clock Mask
If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current
power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is
shown in Table 12-7.
31 30 29 28 27 26 25 24
MASK[31:24]
23 22 21 20 19 18 17 16
MASK[23:16]
15 14 13 12 11 10 9 8
MASK[15:8]
76543210
MASK[7:0]
Table 12-7. Maskable Module Clocks in UC3D.
Bit CPUMASK HSBMASK PBAMASK PBBMASK
0 - FLASHCDW PDCA USBC
1OCD
(1)
PBA bridge INTC HMATRIX
2 - PBB bridge PM FLASHCDW
3 - USBC AST -
4 - PDCA WDT -
5- - EIC -
6- - GPIO -
7 - - USART0 -
8 - - USART1 -
9 - - USART2 -
10 - - SPI -
11 - - TWIM -