Datasheet

114
32133D–11/2011
UC3D
12.7 User Interface
Notes: 1. Latest Reset Source.
2. Latest Wake Source.
Table 12-5. PM Register Memory Map
Offset Register Register Name Access Reset
0x000 Main Clock Control MCCTRL Read/Write 0x00000000
0x004 CPU Clock Select CPUSEL Read/Write 0x00000000
0x008 HSB Clock Select HSBSEL Read-only 0x00000000
0x00C PBA Clock Select PBASEL Read/Write 0x00000000
0x010 PBB Clock Select PBBSEL Read/Write 0x00000000
0x020 CPU Mask CPUMASK Read/Write 0x00000003
0x024 HSB Mask HSBMASK Read/Write 0x0000001F
0x028 PBA Mask PBAMASK Read/Write 0x003FFFFF
0x02C PBB Mask PBBMASK Read/Write 0x00000007
0x040 PBA Divided Mask PBADIVMASK Read/Write 0x0000007F
0x054 Clock Failure Detector Control CFDCTRL Read/Write 0x00000000
0x058 Unlock Register UNLOCK Write-only 0x00000000
0x0C0 PM Interrupt Enable Register IER Write-only 0x00000000
0x0C4 PM Interrupt Disable Register IDR Write-only 0x00000000
0x0C8 PM Interrupt Mask Register IMR Read-only 0x00000000
0x0CC PM Interrupt Status Register ISR Read-only 0x00000000
0x0D0 PM Interrupt Clear Register ICR Write-only 0x00000000
0x0D4 Status Register SR Read-only 0x00000000
0x160 Peripheral Power Control Register PPCR Read/Write 0x00000018
0x180 Reset Cause Register RCAUSE Read-only -
(1)
0x184 Wake Cause Register WCAUSE Read-only -
(2)
0x188 Asyncronous Wake Enable AWEN Read/Write 0x00000000
0x3F8 Configuration Register CONFIG Read-only 0x00000003
0x3FC Version Register VERSION Read-only 0x00000412