Datasheet

111
32133D–11/2011
UC3D
When entering a sleep mode (except Idle mode), all HSB masters must be stopped before
entering the sleep mode. In order to let potential PBx write operations complete, the user should
let the CPU perform a PBx register read operation before issuing the sleep instruction. This will
stall the CPU until pending PBx operations have completed.
12.6.4 Divided PB Clocks
The clock generator in the Power Manager provides divided PBx clocks for use by peripherals
that require a prescaled PBx clock. This is described in the documentation for the relevant mod-
ules. The divided clocks are directly maskable, and are stopped in sleep modes where the PBx
clocks are stopped.
12.6.5 Reset Controller
The Reset Controller collects the various reset sources in the system and generates hard and
soft resets for the digital logic.
The device contains a Power-on Reset (POR) detector, which keeps the system reset until
power is stable. This eliminates the need for external reset circuitry to guarantee stable opera-
tion when powering up the device.
It is also possible to reset the device by pulling the RESET_N pin low. This pin has an internal
pull-up, and does not need to be driven externally during normal operation. Table 12-4 on page
112 lists these and other reset sources supported by the Reset Controller.
Figure 12-3. Reset Controller Block Diagram
In addition to the listed reset types, the JTAG & aWire can keep parts of the device statically
reset. See JTAG and aWire documentation for details.
JTAG
Reset
Controller
RESET_N
Power-on Reset
Detector(s)
OCD
Watchdog Reset
RCAUSE
CPU, HSB, PBx
OCD, AST, WDT,
Clock Generator
Brown-out
Detector
AWIRE