Datasheet

110
32133D–11/2011
UC3D
Notes: 1. The sleep mode index is used as argument for the sleep instruction.
2. Only PB modules operational, as HSB module clocks are stopped.
3. WDT only available if clocked from pre-enabled OSC32K.
12.6.3.4 SleepWalking
In all sleep modes where the PBx clocks are stopped, the device can partially wake up if a PBx
module asynchronously discovers that it needs its clock. Only the requested clocks and clock
sources needed will be started, all other clocks will remain masked to zero. E.g. if the main clock
source is OSC0, only OSC0 will be started even if other clock sources were enabled in normal
mode. Generic clocks can also be started in a similar way. The state where only requested
clocks are running is referred to as SleepWalking.
The time spent to start the requested clock is mostly limited by the startup time of the given clock
source. This allows PBx modules to handle incoming requests, while still keeping the power con-
sumption at a minimum.
When the device is SleepWalking any asynchronous wake-up can wake the device up at any
time without stopping the requested PBx clock.
All requests to start clocks can be masked by writing to the Peripheral Power Control Register
(PPCR), all requests are enabled at reset.
During SleepWalking the interrupt controller clock will be running. If an interrupt is pending when
entering SleepWalking, it will wake the whole device up.
12.6.3.5 Precautions when entering sleep mode
Modules communicating with external circuits should normally be disabled before entering a
sleep mode that will stop the module operation. This will prevent erratic behavior caused by
entering or exiting sleep modes. Please refer to the relevant module documentation for recom-
mended actions.
Communication between the synchronous clock domains is disturbed when entering and exiting
sleep modes. Bus transactions over clock domains affected by the sleep mode are therefore not
recommended. The system may hang if the bus clocks are stopped during a bus transaction.
The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are com-
plete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is
necessary.
Table 12-3. Wake-up Sources
Index
(1)
Sleep Mode Wake-up Sources
0 Idle Synchronous, Asynchronous
1 Frozen Synchronous
(2)
, Asynchronous
2 Standby Asynchronous
3 Stop Asynchronous
4 DeepStop Asynchronous
5 Static Asynchronous
(3)