Datasheet

106
32133D–11/2011
UC3D
12.3 Block Diagram
Figure 12-1. PM Block Diagram
12.4 I/O Lines Description
12.5 Product Dependencies
12.5.1 Interrupt
The PM interrupt line is connected to one of the interrupt controllers internal sources. Using the
PM interrupt requires the interrupt controller to be configured first.
12.5.2 Clock Implementation
In UC3D, the HSB shares source clock with the CPU. Write attempts to the HSB Clock Select
register (HSBSEL) will be ignored, and it will always read the same as the CPU Clock Select
register (CPUSEL).
The PM bus interface clock (CLK_PM) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. If disabled it can only be re-
enabled by a reset.
Table 12-1. I/O Lines Description
Name Description Type Active Level
RESET_N Reset Input Low
Sleep Controller
Synchronous
Clock Generator
Reset Controller
Main Clock Sources
Sleep
Instruction
Power-on Reset
Detector(s)
Resets
Synchronous
clocks
CPU, HSB,
PBx
Interrupts
External Reset Pin
Reset Sources