Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 48 (7x7) 32-Bit 48 MHz I/O number 35

Features

• High Performance, Low Power 32-bit AVR

Microcontroller

– Compact Single-Cycle RISC Instruction Set Including DSP Instructions

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performance

• Up to 61 DMIPS Running at 48MHz from Flash (1 Flash Wait State)

• Up to 34 DMIPS Running at 24MHz from Flash (0 Flash Wait State)

• Multi-Hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 7 Peripheral DMA Channels Improve Speed for Peripheral Communication

• Internal High-Speed Flash

– 128Kbytes, and 64Kbytes Versions

– Single-Cycle Access up to 24MHz

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

–16Kbytes

• Interrupt Controller (INTC)

– Autovectored Low Latency Interrupt Service with Programmable Priority

• External Interrupt Controller (EIC)

• System Functions

– Power and Clock Manager

– SleepWalking

™

Power Saving Control

– Internal System RC Oscillator (RCSYS)

– 32 KHz Oscillator

– Clock Failure Detection

– One Multipurpose Oscillator and two Phase Locked Loop (PLL)

• Windowed Watchdog Timer (WDT)

• Asynchronous Timer (AST) with Real-Time Clock Capability

– Counter or Calendar Mode Supported

• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

• Universal Serial Bus (USB)

– Device 2.0 full speed and low speed

– Flexible End-Point Configuration and Management

– On-chip Transceivers Including Pull-Ups

• Three 16-bit Timer/Counter (TC) Channels

– External Clock Inputs, PWM, Capture and Various Counting Capabilities

• 7 PWM Channels (PWMA)

– 12-bit PWM up to 150MHz Source Clock

• Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independent Baudrate Generator, Support for SPI

– Support for Hardware Handshaking

• One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

– Up to 15 SPI Slaves can be Addressed

32133D–11/2011

32-bit AVR

Microcontroller

ATUC128D3

ATUC64D3

ATUC128D4

ATUC64D4

Summary of content (755 pages)

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Features • High Performance, Low Power 32-bit AVR® Microcontroller • • • • • • • • • • • • • • – Compact Single-Cycle RISC Instruction Set Including DSP Instructions – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performance • Up to 61 DMIPS Running at 48MHz from Flash (1 Flash Wait State) • Up to 34 DMIPS Running at 24MHz from Flash (0 Flash Wait State) Multi-Hierarchy Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 7 Peripheral DMA Channels
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UC3D • • • • • • • • • One Master and One Slave Two-Wire Interfaces (TWI), 400kbit/s I2C-compatible One 8-channel Analog-To-Digital Converter (ADC) One Inter-IC Sound Controller (IISC) with Stereo Capabilities Autonomous Capacitive Touch Button (QTouch®) Capture – Up to 25 Touch Buttons – QWheel® and QSlide® Compatible QTouch® Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch® and QMatrix® Acquisition – Hardware assisted QTouch® Acquisition One Programmable Glue Logic Controller(G
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UC3D 1. Description The UC3D is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies up to 48 MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance. The processor implements a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems.
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UC3D The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using the QTouch® technology. Capacitive touch sensors use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. The CAT module allows up to 25 touch sensors. One touch sensor can be configured to operate autonomously without software interaction,allowing wakeup from sleep modes when activated.
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UC3D 2.
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UC3D 2.2 Configuration Summary Table 2-1.
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UC3D 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2. TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 VDDIO PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 Figure 3-1.
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UC3D TQFP64/QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDIO PA23 PA22 PA21 PA20 PB07 PA29 PA28 PA19 PA18 PB06 PA17 PA16 PA15 PA14 PA13 Figure 3-2.
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UC3D Table 3-1.
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UC3D Table 3-1.
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UC3D 3.2.4 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-4. Oscillator Pinout 48-pin Package 64-pin Package Pin Oscillator Function 30 39 PA18 XIN0 31 40 PA19 XOUT0 22 30 PA11 XIN32 23 31 PA12 XOUT32 3.2.
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UC3D 4. Signal Descriptions The following table gives details on signal name classified by peripheral. Table 4-1.
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UC3D Table 4-1.
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UC3D Table 4-1. Signal Descriptions List EXTTRIG ADCIFD EXTTRIG AD7 - AD0 ADC Inputs Input Analog Power VDDIO Digital I/O Power Supply Power Input 3.0 V to 3.6V. VDDANA Analog Power Supply Power Input 3.0 V to 3.6V ADVREF Analog Reference Voltage Power Input 2.6 V to 3.6 V VDDCORE Core Power Supply Power Input 1.65 V to 1.95 V VDDIN Voltage Regulator Input Power Input 3.0 V to 3.6V VDDOUT Voltage Regulator Output Power Output 1.65 V to 1.
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UC3D independently for each I/O line through the GPIO Controller. After reset, I/O lines default as inputs with pull-up resistors disabled. 4.1.5 4.2 4.2.1 High drive pins Four I/O lines can be used to drive twice current than other I/O capability (see Electrical Characteristics section). 48-pin Package 64-pin Package Pin Name 32 44 PA20 33 45 PA21 34 46 PA22 35 47 PA23 Power Considerations Power Supplies The UC3D has several types of power supply pins: • VDDIO: Powers Digital I/O lines.
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UC3D Figure 4-1. Supply Decoupling 3.3V VDDIN CIN2 CIN1 1.8V 1.8V Regulator VDDOUT COUT2 COUT1 For decoupling recommendations for VDDIO, VDDANA and VDDCORE, please refer to the Schematic checklist. 4.2.3 Regulator Connection The UC3D supports two power supply configurations: • 3.3V single supply mode • 3.3V - 1.8V dual supply mode 4.2.3.1 3.3V Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin).
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UC3D Figure 4-2. 3.3V Single Power Supply mode + 3.0-3.6V - VDDIN VDDIO GND I/O Pins VDDOUT 1.65-1.95V Linear Regulator VDDCORE ADC VDDANA 3.0-3.
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UC3D 4.2.3.2 3.3V + 1.8V Dual Supply Mode In dual supply mode the internal regulator is not used (unconnected), VDDIO is powered by 3.3V supply and VDDCORE is powered by a 1.8V supply as shown in Figure 4-3. Figure 4-3. 3.3V + 1.8V Dual Power Supply Mode. + 3.0-3.6V - VDDIN VDDIO GND I/O Pins VDDOUT Linear Regulator VDDCORE 1.65-1.95V + - VDDANA ADC 3.0-3.6V 4.2.4 CPU, Peripherals, Memories, SCIF, BOD, RCSYS, PLL + - GNDANA Power-up Sequence 4.2.4.
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UC3D See Supply Characteristics table in the Electrical Characteristics chapter for the minimum rise rate value. If the application can not ensure that the minimum rise rate condition for the VDDIN power supply is met, one of the following configuration can be used: •A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V.
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UC3D 5. Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, and instruction set is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 5.
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UC3D The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 5.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced On-Chip Debug (OCD) system, and no caches. Java acceleration hardware is not implemented.
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UC3D OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 5-1. OCD system P ow er/ R eset control A V R 32U C C P U pipeline 5.3.
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UC3D Figure 5-2. The AVR32UC Pipeline Multiply unit MUL IF ID Prefetch unit Decode unit Regfile Read ALU LS 5.3.2 Regfile write ALU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
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UC3D The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 5-1. 5.3.2.4 Instructions with Unaligned Reference Support Instruction Supported Alignment ld.d Word st.
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UC3D 5.4 5.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 5-3.
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UC3D Figure 5-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 5.4.3 Processor States 5.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 5-2. Table 5-2. Overview of Execution Modes, their Priorities and Privilege Levels.
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UC3D Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 5.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC.
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UC3D Table 5-3. 5.
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UC3D the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes.
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UC3D contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 5.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes.
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UC3D The addresses and priority of simultaneous events are shown in Table 5-4 on page 32. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit.
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UC3D Table 5-4.
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UC3D 6. Memories 6.
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UC3D Table 6-2.
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UC3D Table 6-2. Peripheral Address Mapping 0xFFFF6400 GLOC 0xFFFF6800 6.4 AW Glue Logic Controller - GLOC aWire - AW CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus.
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UC3D 7. Boot Sequence This chapter summarizes the boot sequence of the UC3D. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 7.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry for a short time to allow the power to stabilize throughout the device. After reset, the device will use the System RC Oscillator (RCSYS) as clock source.
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UC3D 8. Flash Controller (FLASHCDW) Rev: 1.2.0.0 8.1 Features • • • • • • • • • • • • 8.
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UC3D serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 8.4 8.4.1 Functional Description Bus Interfaces The FLASHCDW has two bus interfaces, one High Speed Bus (HSB) interface for reads from the flash memory and writes to the page buffer, and one Peripheral Bus (PB) interface for issuing commands and reading status from the controller. 8.4.2 Memory Organization The flash memory is divided into a set of pages.
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UC3D in the next cycle, the buffered word is output on the bus, while the next 64-bit location is read from the flash memory. Thus, latency in 1 wait state mode is hidden for sequential fetches. The programmer can select the wait states required by writing to the FWS field in the Flash Control Register (FCR). It is the responsibility of the programmer to select a number of wait states compatible with the clock frequency and timing characteristics of the flash memory.
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UC3D Figure 8-1. Memory Map for the Flash Memories Offset from base address Reserved User Page Reserved 0x0080 0000 Flash data array pw 0 Flash base address Flash with User Page All addresses are byte addresses 8.4.5 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result.
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UC3D flash memory, but will instead update location A%32 in the page buffer. The PAGEN field in the Flash Command (FCMD) register will at the same time be updated with the value A/32. Figure 8-2.
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UC3D buffer value. The only way to change a bit from zero to one is to erase the entire page buffer with the Clear Page Buffer command. The page buffer is not automatically reset after a page write. The programmer should do this manually by issuing the Clear Page Buffer flash command. This can be done after a page write, or before the page buffer is loaded with data to be stored to the flash page. 8.
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UC3D 8.5.1 Write/Erase Page Operation Flash technology requires that an erase must be done before programming. The entire flash can be erased by an Erase All command. Alternatively, pages can be individually erased by the Erase Page command. The User page can be written and erased using the mechanisms described in this chapter. After programming, the page can be locked to prevent miscellaneous write or erase sequences.
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UC3D in FSR is set and the command is cancelled. If the LOCKE bit in FCR is one, an interrupt request is set generated. When the command is complete, the FRDY bit in the Flash Status Register (FSR) is set. If an interrupt has been enabled by writing FCR.FRDY to one, an interrupt request is generated. Two errors can be detected in the FSR register after issuing the command: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register.
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UC3D through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions: Table 8-2. General-purpose Fuses with Special Functions GeneralPurpose fuse number Name Usage 15:0 LOCK Region lock bits. EPFL External Privileged Fetch Lock. Used to prevent the CPU from fetching instructions from external memories when in privileged mode. This bit can only be changed when the security bit is cleared.
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UC3D To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit (WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these commands, together with the number of the fuse to write/erase, performs the desired operation. An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse Byte (PGPFB) instruction. A PGPFB to GP fuse byte 2 is not allowed if the flash is locked by the security bit.
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UC3D 8.8 User Interface Table 8-5.
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UC3D 8.8.1 Name: Flash Control Register FCR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - BRBUF SEQBUF - 7 6 5 4 3 2 1 0 - FWS - - PROGE LOCKE - FRDY • BRBUF: Branch Target Instruction Buffer Enable 0: The Branch Target Instruction Buffer is disabled. 1: The Branch Target Instruction Buffer is enabled.
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UC3D 8.8.2 Name: Flash Command Register FCMD Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit in FSR to be set.
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UC3D Table 8-6. Semantic of PAGEN field in different commands Command PAGEN description Program GP Fuse Byte WriteData[7:0], ByteAddress[2:0] Erase All GP Fuses Not used Quick Page Read Page number Write User Page Not used Erase User Page Not used Quick Page Read User Page Not used High Speed Mode Enable Not used High Speed Mode Disable Not used • CMD: Command This field defines the flash command.
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UC3D 8.8.3 Name: Flash Status Register FSR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 LOCK15 LOCK14 LOCK13 LOCK12 LOCK11 LOCK10 LOCK9 LOCK8 23 22 21 20 19 18 17 16 LOCK7 LOCK6 LOCK5 LOCK4 LOCK3 LOCK2 LOCK1 LOCK0 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - QPRR SECURITY PROGE LOCKE - FRDY • LOCKx: Lock Region x Lock Status 0: The corresponding lock region is not locked.
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UC3D 8.8.4 Name: Flash Parameter Register FPR Access Type: Read-only Offset: 0x0C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 - - - - PSZ 2 1 0 FSZ • PSZ: Page Size The size of each flash page. Table 8-8.
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UC3D • FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 8-9.
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UC3D 8.8.5 Name: Flash Version Register FVR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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UC3D 8.8.
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UC3D 8.8.
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UC3D 8.9 Fuse Settings The flash block contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO). The Flash General Purpose Fuse Register High (FGPFRHI) is not used. Some of these fuses have defined meanings outside the flash controller and are described in this section. In addition to the General Purpose fuses, parts of the flash user page can have a defined meaning outside the flash controller and are described in this section.
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UC3D These fuses should never be programmed. 8.9.1.1 Default Fuse Value The devices are shipped with the FGPFRLO register value: 0xFFF5FFFF: • BODEN fuses set to 11. • BODHYST fuse set to 1. The BOD hysteresis is enabled. • BODLEVEL fuses set to 11111. BOOTPROT fuses set to 010. The bootloader protected size is 8KBytes. • EPFL fuse set to 1. External privileged fetch is not locked. • Reserved fuses set to 1. • LOCK fuses set to 1111111111111111. No region locked.
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UC3D • Configuration word 1 at address 0x808000FC is read first at boot time to know if it should start the ISP process inconditionally and whether it should use the configuration word 2 where further configuration is stored. • Configuration word 2 at address 0x808000F8 stores the I/O conditions that determine which of the ISP and the application to start at the end of the boot process. Please refer to the bootloader documentation for more information.
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UC3D 9. HSB Bus Matrix (HMATRIXB) Rev: 1.3.0.3 9.1 Features • • • • • • • • • 9.
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UC3D To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR.
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UC3D • Undefined Length Burst Arbitration In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected among the following five possibilities: 1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken. 2.
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UC3D rent transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. Other non privileged masters still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses. • Round-Robin Arbitration with Fixed Default Master This is another biased round-robin algorithm. It allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave.
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UC3D 9.5 User Interface Table 9-1.
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UC3D Table 9-1.
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UC3D Table 9-1.
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UC3D 9.5.1 Name: Master Configuration Registers MCFG0...MCFG15 Access Type: Read/Write Offset: 0x00 - 0x3C Reset Value: 0x00000002 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – ULBT • ULBT: Undefined Length Burst Type Table 9-2.
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UC3D 9.5.2 Name: Slave Configuration Registers SCFG0...
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UC3D 9.5.3 Bus Matrix Priority Registers A For Slaves Register Name: PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M7PR 21 20 M5PR 13 12 M3PR 5 4 M1PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M6PR 17 16 M4PR 9 8 M2PR 1 0 M0PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
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UC3D 9.5.4 Name: Priority Registers B For Slaves PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M15PR 21 20 M13PR 13 12 M11PR 5 4 M9PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M14PR 17 16 M12PR 9 8 M10PR 1 0 M8PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
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UC3D 9.5.5 Name: Special Function Registers SFR0...SFR15 Access Type: Read/Write Offset: 0x110 - 0x14C Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SFR 23 22 21 20 SFR 15 14 13 12 SFR 7 6 5 4 SFR • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used.
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UC3D 9.6 9.6.1 Module Configuration Bus Matrix Connections The bus matrix has several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0 register is associated with the CPU Data master interface. Table 9-3.
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UC3D Figure 9-1.
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UC3D 10. Peripheral DMA Controller (PDCA) Rev: 1.2.3.1 10.1 Features • • • • 10.2 Multiple channels Generates transfers between memories and peripherals such as USART and SPI Two address pointers/counters per channel allowing double buffering Ring buffer functionality Overview The Peripheral DMA Controller (PDCA) transfers data between on-chip peripheral modules such as USART, SPI and memories (those memories may be on- and off-chip memories).
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UC3D 10.3 Block Diagram Figure 10-1. PDCA Block Diagram Peripheral 0 Memory HSB to PB Bridge HSB Peripheral Bus HSB High Speed Bus Matrix HSB Interrupt Controller IRQ Peripheral 2 ... Peripheral DMA Controller (PDCA) Peripheral 1 Peripheral (n-1) Handshake Interfaces 10.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 10.4.
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UC3D 10.5 10.5.1 Functional Description Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of handling DMA requests in parallel. Each PDCA channels contains a set of configuration registers which must be configured to start a DMA transfer. In this section the steps necessary to configure one PDCA channel is outlined. The peripheral to transfer data to or from must be configured correctly in the Peripheral Select Register (PSR).
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UC3D 10.5.5 Ring Buffer When Ring Buffer mode is enabled the TCRR and MARR registers will not be cleared when TCR and MAR registers reload. This allows the PDCA to read or write to the same memory region over and over again until the transfer is actively stopped by the user. Ring Buffer mode is enabled by writing a one to the Ring Buffer bit in the Mode Register (MR.RING). 10.5.6 Peripheral Selection The Peripheral Select Register (PSR) decides which peripheral should be connected to the PDCA channel.
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UC3D 10.5.10 Priority If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel zero the highest priority. 10.5.11 Error Handling If the Memory Address Register (MAR) is set to point to an invalid location in memory, an error will occur when the PDCA tries to perform a transfer.
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UC3D 10.6 User Interface 10.6.1 Memory Map Overview Table 10-1. PDCA Register Memory Map Address Range Contents 0x000 - 0x03F DMA channel 0 configuration registers 0x040 - 0x07F DMA channel 1 configuration registers ... ... (0x000 - 0x03F)+m*0x040 DMA channel m configuration registers 0x834 Version register The channels are mapped as shown in Table 10-1. Each channel has a set of configuration registers, shown in Table 10-2, where n is the channel number. 10.6.
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UC3D 10.6.4 Name: Memory Address Register MAR Access Type: Read/Write Offset: 0x000 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 MADDR[31:24] 23 22 21 20 19 MADDR[23:16] 15 14 13 12 MADDR[15:8] 7 6 5 4 MADDR[7:0] • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA.
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UC3D 10.6.5 Name: Peripheral Select Register PSR Access Type: Read/Write Offset: 0x004 + n*0x040 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PID • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA channel.
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UC3D 10.6.6 Name: Transfer Counter Register TCR Access Type: Read/Write Offset: 0x008 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCV[15:8] 7 6 5 4 TCV[7:0] • TCV: Transfer Counter Value Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made.
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UC3D 10.6.7 Name: Memory Address Reload Register MARR Access Type: Read/Write Offset: 0x00C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MARV[31:24] 23 22 21 20 MARV[23:16] 15 14 13 12 MARV[15:8] 7 6 5 4 MARV[7:0] • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a nonzero value.
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UC3D 10.6.8 Name: Transfer Counter Reload Register TCRR Access Type: Read/Write Offset: 0x010 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCRV[15:8] 7 6 5 4 TCRV[7:0] • TCRV: Transfer Counter Reload Value Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value.
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UC3D 10.6.9 Name: Control Register CR Access Type: Write-only Offset: 0x014 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - ECLR 7 6 5 4 3 2 1 0 - - - - - - TDIS TEN • ECLR: Transfer Error Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Error bit in the Status Register (SR.TERR).
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UC3D 10.6.10 Name: Mode Register MR Access Type: Read/Write Offset: 0x018 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - RING - SIZE • RING: Ring Buffer 0:The Ring buffer functionality is disabled. 1:The Ring buffer functionality is enabled.
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UC3D 10.6.11 Name: Status Register SR Access Type: Read-only Offset: 0x01C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TEN • TEN: Transfer Enabled This bit is cleared when the TDIS bit in CR is written to one. This bit is set when the TEN bit in CR is written to one.
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UC3D 10.6.12 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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UC3D 10.6.13 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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UC3D 10.6.14 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x028 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 10.6.15 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x02C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ • TERR: Transfer Error This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR.
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UC3D 10.6.16 Name: PDCA Version Register VERSION Access Type: Read-only Offset: 0x834 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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UC3D 10.7 Module Configuration The specific configuration for each PDCA instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 10-5. PDCA Configuration Feature PDCA Number of channels 7 Table 10-6. Module Clock Name Module name PB Clock Name HSB Clock Name PDCA CLK_PDCA_PB CLK_PDCA_HSB Table 10-7.
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UC3D Table 10-8.
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UC3D 11. Interrupt Controller (INTC) Rev: 1.0.2.5 11.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • Up to 64 groups of interrupts with up to 32 interrupt requests in each group 11.2 Overview The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU.
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UC3D Figure 11-1. INTC Block Diagram Interrupt Controller CPU NMIREQ Masks OR IRRn GrpReqN IREQ63 IREQ34 IREQ33 IREQ32 OR GrpReq1 INT_level, offset IPRn . . . Request Masking ValReq1 INT_level, offset IPR1 . . . INTLEVEL Prioritizer . . . ValReqN SREG Masks I[3-0]M GM AUTOVECTOR IRR1 IREQ31 IREQ2 IREQ1 IREQ0 OR GrpReq0 ValReq0 IPR0 INT_level, offset IRR0 IRR Registers 11.
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UC3D Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted. Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Interrupt Mask (GM).
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UC3D pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared.
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UC3D 11.6 User Interface Table 11-1. INTC Register Memory Map Offset Register Register Name Access Reset 0x000 Interrupt Priority Register 0 IPR0 Read/Write 0x00000000 0x004 Interrupt Priority Register 1 IPR1 Read/Write 0x00000000 ... ... ... ... ... 0x0FC Interrupt Priority Register 63 IPR63 Read/Write 0x00000000 0x100 Interrupt Request Register 0 IRR0 Read-only N/A 0x104 Interrupt Request Register 1 IRR1 Read-only N/A ... ... ... ... ...
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UC3D 11.6.1 Name: Interrupt Priority Registers IPR0...
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UC3D 11.6.2 Name: Interrupt Request Registers IRR0...
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UC3D 11.6.3 Name: Interrupt Cause Registers ICR0...ICR3 Access Type: Read-only Offset: 0x200 - 0x20C Reset Value: N/A 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CAUSE • CAUSE: Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n.
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UC3D 11.7 Module Configuration The specific configuration for each INTC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 11-2. 11.7.1 INTC Clock Name Module Name Clock Name INTC CLK_INTC Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Interrupt Controller (INTC), described in a later chapter.
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UC3D Table 11-3.
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UC3D 12. Power Manager (PM) Rev: 4.1.2.4 12.1 Features • • • • • • 12.
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UC3D 12.3 Block Diagram Figure 12-1. PM Block Diagram Main Clock Sources Synchronous Clock Generator Synchronous clocks CPU, HSB, PBx Interrupts Sleep Controller Sleep Instruction Reset Controller Resets Reset Sources Power-on Reset Detector(s) External Reset Pin 12.4 I/O Lines Description Table 12-1. I/O Lines Description Name Description Type Active Level RESET_N Reset Input Low 12.5 12.5.
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UC3D 12.6 Functional Description 12.6.1 Synchronous Clocks The System RC Oscillator (RCSYS) and a selection of other clock sources can provide the source for the main clock, which is the origin for the synchronous CPU/HSB and PBx module clocks. For details about the other main clock sources, please refer to the Main Clock Control (MCCTRL) register description. The synchronous clocks can run of the main clock and all the 8bit prescaler settings as long as fCPU ≥ fPBx,.
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UC3D Similarly, the PBx clocks can be divided by writing their respective Clock Select (PBxSEL) registers to get the divided PBx frequency: fPBx = fmain / 2(PBSEL+1) The PBx clock frequency can not exceed the CPU clock frequency. The user must select a PBxSEL.PBSEL value greater than or equal to the CPUSEL.CPUSEL value, so that fCPU ≥ fPBx. If the user selects division factors that will result in fCPU< fPBx, the Power Manager will automatically change the PBxSEL.
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UC3D 12.6.3.1 Entering and exiting sleep modes The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains. The modules will be halted regardless of the bit settings in the mask registers. Clock sources can also be switched off to save power. Some of these have a relatively long start-up time, and are only switched off when very low power consumption is required. The CPU and affected modules are restarted when the sleep mode is exited.
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UC3D Table 12-3. Index (1) Wake-up Sources Sleep Mode Wake-up Sources 0 Idle Synchronous, Asynchronous 1 Frozen Synchronous(2), Asynchronous 2 Standby Asynchronous 3 Stop Asynchronous 4 DeepStop Asynchronous 5 Static Asynchronous(3) Notes: 1. The sleep mode index is used as argument for the sleep instruction. 2. Only PB modules operational, as HSB module clocks are stopped. 3. WDT only available if clocked from pre-enabled OSC32K. 12.6.3.
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UC3D When entering a sleep mode (except Idle mode), all HSB masters must be stopped before entering the sleep mode. In order to let potential PBx write operations complete, the user should let the CPU perform a PBx register read operation before issuing the sleep instruction. This will stall the CPU until pending PBx operations have completed. 12.6.4 Divided PB Clocks The clock generator in the Power Manager provides divided PBx clocks for use by peripherals that require a prescaled PBx clock.
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UC3D Table 12-4. Reset Description Reset Source Description Power-on Reset Supply voltage below the Power-on Reset detector threshold voltage VPOT External Reset RESET_N pin asserted Brown-out Reset VDDCORE supply voltage below the Brown-out detector threshold voltage Watchdog Timer See Watchdog Timer documentation OCD See On-Chip Debug documentation Depending on the reset source, when a reset occurs, some parts of the device are not always reset.
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UC3D interrupt is generated if enabled. The MCCTRL register is also changed by hardware to indicate that the main clock comes from RCSYS. 12.6.7 Interrupts The PM has a number of interrupt sources: • AE - Access Error, – A lock protected register is written to without first being unlocked. • CKRDY - Clock Ready: – New Clock Select settings in the CPUSEL/PBxSEL registers have taken effect. (A zero-to-one transition on SR.CKRDY is detected).
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UC3D 12.7 User Interface Table 12-5.
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UC3D 12.7.1 Main Clock Control Name: MCCTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - MCSEL • MCSEL: Main Clock Select Table 12-6. Note: Main clocks in .
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UC3D 12.7.2 CPU Clock Select Name: CPUSEL Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CPUDIV - - - - CPUSEL • CPUDIV, CPUSEL: CPU Division and Clock Select CPUDIV = 0: CPU clock equals main clock. CPUDIV = 1: CPU clock equals main clock divided by 2(CPUSEL+1).
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UC3D 12.7.
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UC3D 12.7.4 PBx Clock Select Name: PBxSEL Access Type: Read/Write Offset: 0x00C-0x010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PBDIV - - - - PBSEL • PBDIV, PBSEL: PBx Division and Clock Select PBDIV = 0: PBx clock equals main clock. PBDIV = 1: PBx clock equals main clock divided by 2(PBSEL+1).
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UC3D 12.7.5 Clock Mask Name: CPUMASK/HSBMASK/PBAMASK/PBBMASK Access Type: Read/Write Offset: 0x020-0x02C Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MASK[31:24] 23 22 21 20 MASK[23:16] 15 14 13 12 MASK[15:8] 7 6 5 4 MASK[7:0] • MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode.
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UC3D Table 12-7. Maskable Module Clocks in UC3D. Bit CPUMASK HSBMASK PBAMASK PBBMASK 12 - - TWIS - 13 - - PWMA - 14 - - IISC - 15 - - TC - 16 SYSTIMER (COMPARE/COUNT REGISTERS CLK) - ADCIFD - 17 - - SCIF - 18 - - FREQM - 19 - - CAT - 20 - - GLOC - 21 - - AW - 22 - - - - 23 - - - - 24 - - - - 25 - - - - 31:25 - - - - Note: 1. This bit must be one if the user wishes to debug the device with a JTAG debugger.
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UC3D 12.7.6 Divided Clock Mask Name: PBADIVMASK Access Type: Read/Write Offset: 0x040 Reset Value: 0x0000007F 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - MASK[6:0] • MASK: Clock Mask If bit n is written to zero, the clock divided by 2(n+1) is stopped. If bit n is written to one, the clock divided by 2(n+1) is enabled according to the current power mode.
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UC3D 12.7.7 Clock Failure Detector Control Register Name: CFDCTRL Access Type: Read/Write Offset: 0x054 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - OCPEN CFDEN • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes.
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UC3D 12.7.8 PM Unlock Register Name: UNLOCK Access Type: Write-Only Offset: 0x058 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
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UC3D 12.7.9 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0C0 Reset Value: - 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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UC3D 12.7.10 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0C4 Reset Value: - 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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UC3D 12.7.11 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x0C8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one.
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UC3D 12.7.12 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x0CC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one.
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UC3D 12.7.13 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0D0 Reset Value: - 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR.
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UC3D 12.7.14 Status Register Name: SR Access Type: Read-only Offset: 0x0D4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD • AE: Access Error 0: No access error has occured. 1: A write to lock protected register without unlocking it has occured.
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UC3D 12.7.
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UC3D 12.7.
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UC3D 12.7.17 Wake Cause Register Name: WCAUSE Access Type: Read-only Offset: 0x184 Reset Value: Latest Wake Source 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - AST EIC 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - TWIS USBC A bit in this register is set on wake up caused by the corresponding peripheral.
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UC3D 12.7.18 Asynchronous Wake Up Enable Register Name: AWEN Access Type: Read/Write Offset: 0x188 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - TWIS USBC Each bit in this register corresponds to an asynchronous wake up. 0: The correcponding wake up is disabled. 1: The corresponding wake up is enabled.
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UC3D 12.7.19 Configuration Register Name: CONFIG Access Type: Read-Only Offset: 0x3F8 Reset Value: 0x000000003 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 HSBPEVC OCP - - PBD PBC PBB PBA This register shows the configuration of the PM. • HSBPEVC:HSB PEVC Clock Implemented 0: HSBPEVC not implemented. 1: HSBPEVC implemented.
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UC3D 12.7.20 Version Register Name: VERSION Access Type: Read-Only Offset: 0x3FC Reset Value: 0x00000412 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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UC3D 12.8 Module Configuration The specific configuration for each PM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the “Synchronous Clocks”, “Peripheral Clock Masking” and “Sleep Modes” sections for details. Table 12-8. Power Manager Clock Name Module Name Clock Name PM CLK_PM Table 12-9. Register Reset Values Register Reset Value VERSION 0x00000412 Table 12-10.
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UC3D 13. System Control Interface (SCIF) Rev: 1.0.2.0 13.1 Features • • • • • • • • • • 13.2 Controls integrated oscillators and Phase Locked Loops (PLLs) Supports crystal oscillator 0.
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UC3D 13.4.3 Debug Operation The SCIF module does not interact with debug operations. 13.4.4 Clocks The SCIF controls all oscillators on the part. Those oscillators can then be used as sources for for generic clocks (handled by the SCIF) and for the CPU and peripherals. (In this case, selection of source is done by the Power Manager.) 13.5 13.5.
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UC3D 13.5.2 32KHz Oscillator Operation The 32KHz oscillator operates as described for the Oscillator above. The 32 KHz oscillator is used as source clock for the Asynchronous Timer and the Watchdog Timer. The 32KHz oscillator can be used as source for the generic clocks. The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32. The oscillator is an ultra-low power design and remains enabled in all sleep modes.
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UC3D Figure 13-2. PLL with control logic and filters PLLMUL Output Divider Osc0 clock Input Divider PLLDIV 13.5.3.1 PLL Mask PLL clock LOCK PLLEN PLLOPT Enabling the PLL PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source. The PLLMUL and PLLDIV bit fields must be written with the multiplication and division factors. The PLLn.PLLOPT field should be set to proper values according to the PLL operating frequency.
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UC3D Figure 13-3. Generic clock generation Sleep Controller 0 Mask Divider OSCSEL 13.5.4.1 DIV Generic Clock 1 DIVEN CEN Enabling a generic clock A generic clock is enabled by writing the CEN bit in GCCTRL to one. Each generic clock can individually select a clock source by setting the OSCSEL bits. The source clock can optionally be divided by writing DIVEN to one and the division factor to DIV, resulting in the output frequency: fGCLK = fSRC / (2*(DIV+1)) 13.5.4.
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UC3D Table 13-2. Generic clock allocation Clock number 13.5.5 Function 3 USB clock (48 MHz) 4 PWMA 5 IISC 6 AST 7 - 8 ADCIFD Brown Out Detection (BOD) The Brown-Out Detector (BOD) monitors the internal voltage regulator output and compares the voltage to the brown-out detection level, as set in BOD.LEVEL. The BOD is disabled by default, but can be enabled either by software or by flash fuses.
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UC3D Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to those registers. To prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the UNLOCK register description. 13.5.8 System RC Oscillator (RCSYS) The system RC oscillator (RCSYS) has a 3 cycles startup time, and is always available except in Static mode.
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UC3D 13.6 User Interface Table 13-3.
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UC3D 13.6.1 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - PLL1_LOCK LOST PLL0_LOCK LOST BODDET PLL1_LOCK PLL0_LOCK OSC32RDY OSC0RDY Writing a zero to a bit in this register has no effect.
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UC3D 13.6.2 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - PLL1_LOCK LOST PLL0_LOCK LOST BODDET PLL1_LOCK PLL0_LOCK OSC32RDY OSC0RDY Writing a zero to a bit in this register has no effect.
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UC3D 13.6.3 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x0008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - PLL1_LOCK LOST PLL0_LOCK LOST BODDET PLL1_LOCK PLL0_LOCK OSC32RDY OSC0RDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 13.6.4 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x000C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - PLL1_LOCK LOST PLL0_LOCK LOST BODDET PLL1_LOCK PLL0_LOCK OSC32RDY OSC0RDY 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending.
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UC3D 13.6.5 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - PLL1_LOCK LOST PLL0_LOCK LOST BODDET PLL1_LOCK PLL0_LOCK OSC32RDY OSC0RDY Writing a zero to a bit in this register has no effect.
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UC3D 13.6.6 Power and Clocks Status Register Name: PCLKSR Access Type: Read-only Offset: 0x0014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - PLL1_LOCK LOST PLL0_LOCK LOST BODDET PLL1_LOCK PLL0_LOCK OSC32RDY OSC0RDY • AE: SCIF Access Error value 0: No access error has occurred on the SCIF.
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UC3D 13.6.7 Unlock Register Name: UNLOCK Access Type: Write-only Offset: 0x0018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
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UC3D 13.6.
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UC3D Table 13-4. PLLOPT Fields Description Description PLLOPT[0]: VCO frequency 0 80MHz
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UC3D 13.6.9 Oscillator Control Register Name: OSCCTRL0 Access Type: Read/Write Offset: 0x0024 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - OSCEN 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 3 1 0 - - - - AGC STARTUP 2 GAIN MODE • OSCEN 0: Disable the Oscillator. 1: Enable the Oscillator • STARTUP: Oscillator Startup Time Select startup time for the oscillator. Table 13-5.
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UC3D Table 13-5. Startup time for oscillators 0 STARTUP Number of RC oscillator clock cycle Approximative Equivalent time (RCSYS = 115 kHz) 13 512 4.5 ms 14 1024 9 ms 15 Reserved Reserved • AGC: Automatic Gain Control For test purposes • GAIN: Gain 0 Oscillator is used with gain G0 (XIN from 0.4 MHz to 12.0 MHz) 1 Oscillator is used with gain G1 (XIN from 12.0 MHz to 16.0 MHz) 2 Oscillator is used with gain G2 (XIN from 16.0 MHz to 20.
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UC3D 13.6.10 1.8V BOD Control Register Name: BOD Access Type: Read/Write Offset: 0x0028 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - HYST CTRL 1 0 LEVEL • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes.
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UC3D Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details.
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UC3D 13.6.11 Bandgap Calibration Register Name: BGCR Access Type: Read/Write Offset: 0x002C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 - - - - - 0 CALIB • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes.
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UC3D 13.6.12 Voltage Regulator Calibration Register Name: VREGCR Access Type: Read/Write Offset: 0x0030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 - - - - - SLEEPCALIB 2 1 0 CALIB • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes.
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UC3D 13.6.13 Voltage Regulator Control Register Name: VREGCTRL Access Type: Read/Write Offset: 0x0034 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - DMD - 7 6 5 4 3 2 1 0 - - - - - - - - • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes.
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UC3D 13.6.14 RCSYS Calibration Register Name: RCCR Access Type: Read/Write Offset: 0x0038 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 CALIB[9:8] 1 0 CALIB[7:0] • FCD: Flash Calibration Done Set to 1 when CALIB field has been updated by the Flash fuses after a reset. 0: The flash calibration will be redone after any reset.
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UC3D 13.6.15 32KHz Oscillator Control Register Name: OSCCTRL32 Access Type: Read/Write Offset: 0x003C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 10 - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - OSC32EN STARTUP 9 8 MODE Note: This register is only reset by Power-On Reset • STARTUP: Oscillator Startup Time Select startup time for 32 KHz oscillator Table 13-7.
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UC3D • MODE: Oscillator Mode Table 13-8. MODE Operation mode for 32 KHz oscillator Description 0 External clock connected to XIN32, XOUT32 can be used as I/O (no crystal) 1 2-pin Crystal mode. Crystal is connected to XIN32/XOUT32. 2 2-pin Crystal and I-Current mode. Crystal is connected to XIN32/XOUT32. 3 Reserved • OSC32EN: Enable the 32 KHz oscillator 0: 32 KHz Oscillator is disabled 1: 32 KHz Oscillator is enabled Note that this register is protected by a lock.
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UC3D 13.6.16 120MHz RC Oscillator Configuration Register Name: RC120MCR Access Type: Read/Write Offset: 0x0044 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - EN • EN: RC120M Enable 0: Clock is stopped. 1: Clock is running. Note that this register is protected by a lock.
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UC3D 13.6.17 General Purpose Low-power Register 0/1 Name: GPLP0,1 Access Type: Read/Write Offset: 0x0048, 0x004C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the bits of these registers untouched.
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UC3D 13.6.18 Generic Clock Control Name: GCCTRL Access Type: Read/Write Offset: 0x0060-0x0080 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 DIV 15 14 13 12 OSCSEL 7 6 5 4 3 2 1 0 - - - - - - DIVEN CEN There is one GCCTRL register per generic clock in the design. • DIV: Division Factor • OSCSEL: Generic Clock Source Selection Table 13-9.
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UC3D • CEN: Clock Enable 0: Clock is stopped. 1: Clock is running.
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UC3D 13.6.19 PLL Interface Version Register Name: PLLVERSION Access Type: Read-Only Offset: 0x03D4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 13.6.20 Oscillator 0 Interface Version Register Name: OSCVERSION Access Type: Read-only Offset: 0x03D8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
PAGE 170
UC3D 13.6.21 1.8V BOD Interface Version Register Name: BODVERSION Access Type: Read-Only Offset: 0x03DC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 13.6.22 Voltage Regulator Interface Version Register Name: VREGVERSION Access Type: Read-Only Offset: 0x03E0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 13.6.23 RCSYS Interface Version Register Name: RCCRVERSION Access Type: Read-Only Offset: 0x03E4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 13.6.24 32KHz Oscillator Interface Version Register Name: OSC32VERSION Access Type: Read-only Offset: 0x03E8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 13.6.25 120MHz RC Oscillator Interface Version Register Name: RC120MVERSION Access Type: Read-only Offset: 0x03F0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 13.6.26 GPLP Version Register Name: GPLPVERSION Access Type: Read-only Offset: 0x03F4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 13.6.27 Generic Clock Interface Version Register Name: GCLKVERSION Access Type: Read-Only Offset: 0x03F8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 13.6.28 SCIF Version Register Name: VERSION Access Type: Read-only Offset: 0x03FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:0] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 13.7 Module Configuration The specific configuration for each SCIF instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 13-10. SCIF Clock Name Module Name Clock Name SCIF CLK_SCIF Table 13-11.
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UC3D 14. Asynchronous Timer (AST) Rev: 3.1.0.1 14.1 Features • 32-bit counter with 32-bit prescaler • Clocked Source – System RC oscillator (RCSYS) – 32KHz crystal oscillator (OSC32K) – PB clock – Generic clock (GCLK) • Optional calendar mode supported • Periodic interrupt(s) supported • Alarm interrupt(s) supported – Optional clear on alarm 14.2 Overview The Asynchronous Timer (AST) enables periodic interrupts, as well as interrupts at a specified time in the future.
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UC3D 14.3 Block Diagram Figure 14-1. Asynchronous Timer Block diagram CLK_AST CONTROL REGISTER CLK_AST CSSEL EN OSC32 RCSYS PB clock GCLK CLK_AST_PRSC CLK_AST Wake Control COUNTER VALUE Wake PSEL 32-bit Prescaler CLK_AST_CNT 32-bit Counter others 14.
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UC3D • Peripheral Bus clock (PB clock). This is the clock of the peripheral bus the AST is connected to. • Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be enabled before use, and remains enabled in sleep modes when the PB clock is active. 14.4.3 Interrupts The AST interrupt request lines are connected to the interrupt controller. Using the AST interrupts requires the interrupt controller to be programmed first. 14.4.
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UC3D To change the clock: • Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero • Write the selected value to CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero • Write a one to CLOCK.CEN to enable the clock, without changing the CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero 14.5.2 Basic Operation 14.5.2.1 Prescaler When the AST is enabled, the 32-bit prescaler will increment on the rising edge of CLK_AST_PRSC.
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UC3D (e.g. 2000). The date is automatically compensated for leap years, assuming every year divisible by 4 is a leap year. All interrupts work the same way in calendar mode as in counter mode. However, the Alarm Register (ARn) must be written in time/date format for the alarm to trigger correctly. 14.5.
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UC3D Because of synchronization, the transfer of the INSEL value will not happen immediately. When changing/setting the INSEL value, the user must make sure that the prescaler bit number INSEL will not have a 0-to-1 transition before the INSEL value is transferred to the register. In that case, the first periodic interrupt after the change will not be triggered. 14.5.3.2 Alarm interrupt The AST can also generate alarm interrupts.
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UC3D 14.6 User Interface Table 14-1.
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UC3D 14.6.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 12 11 10 9 8 - - - - - - CA1 CA0 7 6 5 4 3 2 1 0 - - - - - CAL PCLR EN PSEL When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as zero.
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UC3D 14.6.2 Name: Counter Value CV Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 19 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as zero. • VALUE: AST Value The current value of the AST counter.
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UC3D 14.6.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY CLKBUSY - - READY BUSY 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF • CLKRDY: Clock Ready This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the SR.
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UC3D 14.6.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set, writes to this register will be discarded. Writing a zero to a bit in this register has no effect.
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UC3D 14.6.5 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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UC3D 14.6.6 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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UC3D 14.6.7 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 14.6.8 Name: Wake Enable Register WER Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. This register enables the wakeup signal from the AST.
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UC3D 14.6.9 Name: Alarm Register 0 AR0 Access Type: Read/Write Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 19 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: Alarm Value When the counter reaches this value, an alarm is generated.
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UC3D 14.6.10 Name: Alarm Register 1 AR1 Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 19 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: Alarm Value When the counter reaches this value, an alarm is generated.
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UC3D 14.6.11 Name: Periodic Interval Register 0 PIR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - INSEL When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
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UC3D 14.6.12 Name: Periodic Interval Register 1 PIR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - INSEL When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
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UC3D 14.6.13 Name: Clock Control Register CLOCK Access Type: Read/Write Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CEN CSSEL When writing to this register, follow the sequence in Section 14.5.1 on page 181.
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UC3D 14.6.14 Name: Calendar Value CALV Access Type: Read/Write Offset: 0x54 Reset Value: 0x00000000 31 30 29 28 27 26 25 YEAR 23 22 21 MONTH[3:2] 20 MONTH[1:0] 15 19 18 17 DAY 14 13 12 6 16 HOUR[4] 11 10 HOUR[3:0] 7 24 9 8 1 0 MIN[5:2] 5 4 3 MIN[1:0] 2 SEC When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • YEAR: Year Current year. The year is considered a leap year if YEAR[1:0] = 0.
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UC3D 14.6.15 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0xF0 Reset Value: - 31 30 29 - - - 23 22 21 - - - 15 14 13 12 11 10 PIR1WA PIR0WA - NUMPIR - - 7 6 5 4 3 2 - 28 27 26 25 24 17 16 9 8 PER1VALUE 20 19 18 PER0VALUE - NUMAR 1 0 - - • NUMAR: Number of Alarm Comparators 0: Zero alarm comparators. 1: One alarm comparator. 2: Two alarm comparators. • NUMPIR: Number of Periodic Comparators 0: One periodic comparator.
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UC3D 14.6.16 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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UC3D 14.7 Module Configuration The specific configuration for each AST instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 14-3. Module Configuration Feature AST Number of alarm comparators 1 Number of periodic comparators 1 Digital tuner Off Table 14-4.
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UC3D 15. Watchdog Timer (WDT) Rev: 4.1.0.0 15.1 Features • • • • • 15.2 Watchdog Timer counter with 32-bit counter Timing window watchdog Clocked from system RC oscillator or the 32 KHz crystal oscillator Configuration lock WDT may be enabled at reset by a fuse Overview The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable.
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UC3D 15.4.1 Power Management When the WDT is enabled, the WDT remains clocked in all sleep modes. It is not possible to enter sleep modes where the source clock of CLK_CNT is stopped. Attempting to do so will result in the device entering the lowest sleep mode where the source clock is running, leaving the WDT operational. Please refer to the Power Manager chapter for details about sleep modes. After a watchdog reset the WDT bit in the Reset Cause Register (RCAUSE) in the Power Manager will be set. 15.4.
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UC3D To change the clock for the WDT the following steps need to be taken. Note that the WDT should always be disabled before changing the CLK_CNT source: 1. Write a zero to the Clock Enable (CEN) bit in the CTRL Register, leaving the other bits as they are in the CTRL Register. This will stop CLK_CNT. 2. Read back the CTRL Register until the CEN bit reads zero. The clock has now been stopped. 3.
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UC3D Figure 15-2. Basic Mode WDT Timing Diagram, normal operation. t= t 0 T psel T im e o u t W rite o n e to C L R .W D T C L R W a tc h d o g re s e t If the WDT counter is not cleared within Tpsel a watchdog reset will be issued at the end of Tpsel, see Figure 15-3 on page 206. Figure 15-3. Basic Mode WDT Timing Diagram, no clear within Tpsel. t= t 0 T p se l T im eo ut W rite one to C LR .W D T C LR W atchdo g re set 15.5.1.
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UC3D The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT timeout period Ttimeout = Ttban + Tpsel = (2(TBAN+1) + 2(PSEL+1)) / fclk_cnt where Ttban sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and the code will start executing form the boot vector, see Figure 15-5 on page 207. The WDT counter will be cleared. Writing a one to the CLR.
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UC3D 15.5.3 Disabling the WDT The WDT is disabled by writing a zero to the CTRL.EN bit. When disabling the WDT no other bits in the CTRL Register should be changed until the CTRL.EN bit reads back as zero. If the CTRL.CEN bit is written to zero, the CTRL.EN bit will never read back as zero if changing the value from one to zero. 15.5.4 Flash Calibration The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse.
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UC3D 15.6 User Interface Table 15-1. Note: WDT Register Memory Map Offset Register Register Name Access Reset 0x000 Control Register CTRL Read/Write 0x00010080 0x004 Clear Register CLR Write-only 0x00000000 0x008 Status Register SR Read-only 0x00000003 0x3FC Version Register VERSION Read-only -(1) 1. The reset value for this register is device specific. Please refer to the Module Configuration section at the end of this chapter.
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UC3D 15.6.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00010080 31 30 29 28 27 26 25 24 19 18 17 16 CSSEL CEN 9 8 KEY 23 22 21 - 20 TBAN 15 14 13 12 11 10 - - - 7 6 5 4 3 2 1 0 FCD - - - SFV MODE DAR EN PSEL • KEY • • • • • • • This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads as zero.
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UC3D • DAR: WDT Disable After Reset 0: After a watchdog reset, the WDT will still be enabled. 1: After a watchdog reset, the WDT will be disabled. • EN: WDT Enable 0: WDT is disabled. 1: WDT is enabled. After writing to this bit the read back value will not change until the WDT is enabled/disabled. This due to internal synchronization.
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UC3D 15.6.2 Name: Clear Register CLR Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - WDTCLR When the Watchdog Timer is enabled, this Register must be periodically written within the window time frame or within the watchdog timeout period, to prevent a watchdog reset.
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UC3D 15.6.3 Name: Status Register SR Access Type: Read-only Offset: 0x008 Reset Value: 0x00000003 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - CLEARED WINDOW • CLEARED: WDT Counter Cleared This bit is cleared when writing a one to the CLR.WDTCLR bit. This bit is set when clearing the WDT counter is done.
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UC3D 15.6.4 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 15.7 Module Configuration The specific configuration for each WDT instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 15-2. Module clock name Module name Clock name WDT CLK_WDT Table 15-3.
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UC3D 16. External Interrupt Controller (EIC) Rev: 3.0.2.0 16.1 Features • • • • • • • 16.2 Dedicated interrupt request for each interrupt Individually maskable interrupts Interrupt on rising or falling edge Interrupt on high or low level Asynchronous interrupts for sleep modes without clock Filtering of interrupt lines Non-Maskable NMI interrupt Overview The External Interrupt Controller (EIC) allows pins to be configured as external interrupts.
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UC3D 16.4 I/O Lines Description Table 16-1. 16.5 I/O Lines Description Pin Name Pin Description Type NMI Non-Maskable Interrupt Input EXTINTn External Interrupt Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 16.5.1 I/O Lines The external interrupt pins (EXTINTn and NMI) may be multiplexed with I/O Controller lines.
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UC3D Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL registers. Each interrupt has a bit INTn in each of these registers. Writing a zero to the INTn bit in the MODE register enables edge triggered interrupts, while writing a one to the bit enables level triggered interrupts.
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UC3D Figure 16-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on Figure 16-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on 16.6.3 Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in Section 16.6.
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UC3D When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be updated on the first rising edge of CLK_SYNC. Figure 16-4. Timing Diagram, Asynchronous Interrupts C LK _SYN C C LK _SYN C E X T IN T n /N M I 16.6.5 E X T IN T n /N M I IS R .IN T n : r is in g E D G E o r h ig h LEVEL IS R .
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UC3D 16.7 User Interface Table 16-2.
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UC3D 16.7.
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UC3D 16.7.
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UC3D 16.7.
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UC3D 16.7.4 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - INT30 INT29 INT28 INT27 INT26 INT25 INT24 23 22 21 20 19 18 17 16 INT23 INT22 INT21 INT20 INT19 INT18 INT17 INT16 15 14 13 12 11 10 9 8 INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 NMI • INTn: External Interrupt n 0: An interrupt event has not occurred.
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UC3D 16.7.
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UC3D 16.7.6 Name: Mode Register MODE Access Type: Read/Write Offset: 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - INT30 INT29 INT28 INT27 INT26 INT25 INT24 23 22 21 20 19 18 17 16 INT23 INT22 INT21 INT20 INT19 INT18 INT17 INT16 15 14 13 12 11 10 9 8 INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 NMI • INTn: External Interrupt n 0: The external interrupt is edge triggered.
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UC3D 16.7.
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UC3D 16.7.
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UC3D 16.7.9 Filter Register Name: FILTER Access Type: Read/Write Offset: 0x020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - INT30 INT29 INT28 INT27 INT26 INT25 INT24 23 22 21 20 19 18 17 16 INT23 INT22 INT21 INT20 INT19 INT18 INT17 INT16 15 14 13 12 11 10 9 8 INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 NMI • INTn: External Interrupt n 0: The external interrupt is not filtered.
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UC3D 16.7.
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UC3D 16.7.
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UC3D 16.7.12 Enable Register Name: EN Access Type: Write-only Offset: 0x030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - INT30 INT29 INT28 INT27 INT26 INT25 INT24 23 22 21 20 19 18 17 16 INT23 INT22 INT21 INT20 INT19 INT18 INT17 INT16 15 14 13 12 11 10 9 8 INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 NMI • INTn: External Interrupt n Writing a zero to this bit has no effect.
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UC3D 16.7.13 Disable Register Name: DIS Access Type: Write-only Offset: 0x034 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - INT30 INT29 INT28 INT27 INT26 INT25 INT24 23 22 21 20 19 18 17 16 INT23 INT22 INT21 INT20 INT19 INT18 INT17 INT16 15 14 13 12 11 10 9 8 INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 NMI • INTn: External Interrupt n Writing a zero to this bit has no effect.
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UC3D 16.7.
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UC3D 16.7.15 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 16.8 Module Configuration The specific configuration for each EIC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 16-3. Module Configuration Feature EIC Number of external interrupts, including NMI 9 Table 16-4. Module Clock Name Module Name Clock Name EIC CLK_EIC Table 16-5.
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UC3D 17. Frequency Meter (FREQM) Rev: 3.1.0.1 17.1 Features • • • • 17.2 Accurately measures a clock frequency Selectable reference clock A selectable clock can be measured Ratio can be measured with 24-bit accuracy Overview The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock. 17.3 Block Diagram Figure 17-1. Frequency Meter Block Diagram CLKSEL START CLK_MSR Counter VALUE CLK_REF Timer Trigger REFSEL 17.
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UC3D 17.4.2 Clocks The clock for the FREQM bus interface (CLK_FREQM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the FREQM before disabling the clock, to avoid freezing the FREQM ia an undefined state. A set of clocks can be selected as reference (CLK_REF) and another set of clocks can be selected for measurement (CLK_MSR).
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UC3D • Write a zero to the MODE.REFCEN to disable he clock, without changing the other bits/fields in the Mode register. • Wait until the SR.RCLKBUSY bit reads as zero. 17.5.1.1 17.5.2 Cautionary note Note that if clock selected as source for CLK_REF is stopped during a measurement, this will not be detected by the FREQM. The BUSY bit in the STATUS register will never be cleared, and the DONE interrupt will never be triggered.
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UC3D 17.6 User Interface Table 17-1.
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UC3D 17.6.1 Name: Control Register CTRL Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - START • START Writing a zero to this bit has no effect. Writing a one to this bit will start a measurement.
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UC3D 17.6.2 Name: Mode Register MODE Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 REFCEN - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 CLKSEL 12 11 10 9 8 2 1 0 REFNUM 7 6 5 4 3 - - - - - REFSEL • REFCEN: Reference Clock Enable 0: The reference clock is disabled 1: The reference clock is enabled • CLKSEL: Clock Source Selection Selects the source for CLK_MSR.
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UC3D 17.6.3 Status Register Name: STATUS Access Type: Read-only Offset: 0x008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKBUSY BUSY • RCLKBUSY: FREQM Reference Clock Status 0: The FREQM ref clk is ready, so a measurement can start. 1: The FREQM ref clk is not ready, so a measurement should not be started.
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UC3D 17.6.4 Value Register Name: VALUE Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] • VALUE: Result from measurement.
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UC3D 17.6.5 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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UC3D 17.6.6 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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UC3D 17.6.7 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 17.6.8 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x01C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending.
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UC3D 17.6.9 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect.
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UC3D 17.6.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 17.7 Module Configuration The specific configuration for each FREQM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 17-2. Module Clock Name Module Name FREQM Table 17-3. Table 17-4.
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UC3D 18. General-Purpose Input/Output Controller (GPIO) Rev: 2.1.2.5 18.1 Features • • • • • • 18.
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UC3D 18.4 I/O Lines Description Pin Name Description Type GPIOn GPIO pin n Digital 18.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 18.5.1 Power Management If the CPU enters a sleep mode that disables clocks used by the GPIO, the GPIO will stop functioning and resume operation after the system wakes up from sleep mode.
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UC3D 18.6 Functional Description The GPIO controls the I/O pins of the microcontroller. The control logic associated with each pin is shown in the figure below. Figure 18-2. Overview of the GPIO PUER* ODER 1 0 Periph. Func. A Output Pullup 0 Periph.Func. B Periph. Func. C 1 ....
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UC3D 18.6.1 Basic Operation 18.6.1.1 Module Configuration The GPIO user interface registers are organized into ports and each port controls 32 different GPIO pins. Most of the registers supports bit wise access operations such as set, clear and toggle in addition to the standard word access. For details regarding interface registers, refer to Section 18.7. 18.6.1.2 Available Features The GPIO features implemented are device dependent, and not all functions are implemented on all pins.
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UC3D 18.6.2 Advanced Operation 18.6.2.1 Peripheral I/O Pin Control When a GPIO pin is assigned to a peripheral function, i.e. the corresponding bit in GPER is zero, output and output enable is controlled by the selected peripheral pin. In addition the peripheral may control some or all of the other GPIO pin functions listed in Table 18-1, if the peripheral supports those features. All pin features not controlled by the selected peripheral is controlled by the GPIO.
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UC3D Register (IER). The module can be configured to generate an interrupt whenever a pin changes value, or only on rising or falling edges. This is controlled by the Interrupt Mode Registers (IMRn). Interrupts on a pin can be enabled regardless of the GPIO pin being controlled by the GPIO or assigned to a peripheral function. An interrupt can be generated on each GPIO pin. These interrupt generators are further grouped into groups of eight and connected to the interrupt controller.
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UC3D Figure 18-5. Interrupt Timing with Glitch Filter Enabled CLK_GPIO Pin Level IFR 18.6.2.7 CPU Local Bus The CPU Local Bus can be used for application where low latency read and write access to the Output Value Register (OVR) and Output Drive Enable Register (ODER) is required. The CPU Local Bus allows the CPU to configure the mentioned GPIO registers directly, bypassing the shared Peripheral Bus (PB).
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UC3D 18.7 User Interface The GPIO controller manages all the GPIO pins on the 32-bit AVR microcontroller. The pins are managed as 32-bit ports that are configurable through a Peripheral Bus (PB) interface. Each port has a set of configuration registers. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports is product specific. Figure 18-6. Port Configuration Registers 0x0000 Port 0 Configuration Registers 0x0200 Port 1 Configuration Registers 0x0400 ….
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UC3D ten to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g. IFR), not all access methods are permitted. Note that for ports with less than 32 bits, the corresponding control registers will have unused bits. This is also the case for features that are not implemented for a specific pin. Writing to an unused bit will have no effect. Reading unused bits will always return 0. 18.7.
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UC3D Table 18-2. GPIO Register Memory Map Offset Register Function Register Name Access 0x02C Peripheral Mux Register 1 Toggle PMR1T Write-only Reset - (1) Config.
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UC3D Table 18-2. GPIO Register Memory Map Offset Register Function Register Name Access Reset Config.
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UC3D 18.7.4 Name: GPIO Enable Register GPER Access: Read/Write, Set, Clear, Toggle Offset: 0x000, 0x004, 0x008, 0x00C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: GPIO Enable 0: A peripheral function controls the corresponding pin.
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UC3D 18.7.
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UC3D 18.7.
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UC3D 18.7.
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UC3D 18.7.8 Name: Output Driver Enable Register ODER Access: Read/Write, Set, Clear, Toggle Offset: 0x040, 0x044, 0x048, 0x04C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Driver Enable 0: The output driver is disabled for the corresponding pin.
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UC3D 18.7.9 Name: Output Value Register OVR Access: Read/Write, Set, Clear, Toggle Offset: 0x050, 0x054, 0x058, 0x05C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Value 0: The value to be driven on the GPIO pin is 0.
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UC3D 18.7.10 Name: Pin Value Register PVR Access: Read-only Offset: 0x060, 0x064, 0x068, 0x06C Reset Value: Depending on pin states 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pin Value 0: The GPIO pin is at level zero. 1: The GPIO pin is at level one.
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UC3D 18.7.
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UC3D 18.7.12 Name: Interrupt Enable Register IER Access: Read/Write, Set, Clear, Toggle Offset: 0x090, 0x094, 0x098, 0x09C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Enable 0: Interrupt is disabled for the corresponding pin.
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UC3D 18.7.
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UC3D 18.7.
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UC3D 18.7.15 Name: Glitch Filter Enable Register GFER Access: Read/Write, Set, Clear, Toggle Offset: 0x0C0, 0x0C4, 0x0C8, 0x0CC Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Glitch Filter Enable 0: Glitch filter is disabled for the corresponding pin.
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UC3D 18.7.16 Name: Interrupt Flag Register IFR Access: Read, Clear Offset: 0x0D0, 0x0D8 Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Flag 0: No interrupt condition has been detected on the corresponding pin.
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UC3D 18.7.17 Name: Lock Register LOCK Access: Read/Write, Set, Clear, Toggle Offset: 0x1A0, 0x1A4, 0x1A8, 0x1AC Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Lock State 0: Pin is unlocked.
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UC3D 18.7.18 Name: Unlock Register UNLOCK Access: Write-only Offset: 0x1E0 Reset Value: - 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 - - - - - - 7 6 5 4 3 2 8 OFFSET 1 0 OFFSET • OFFSET: Register Offset This field must be written with the offset value of the LOCK, LOCKC or LOCKT register to unlock. This offset must also include the port offset for the register to unlock.
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UC3D 18.7.19 Name: Access Status Register ASR Access: Read/Write Offset: 0x1E4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - AE • AE: Access Error This bit is set when a write to a locked register occurs. This bit can be written to 0 by software.
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UC3D 18.7.20 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x1F8 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PARAMETER 23 22 21 20 PARAMETER 15 14 13 12 PARAMETER 7 6 5 4 PARAMETER • PARAMETER: 0: The corresponding pin is not implemented in this GPIO port. 1: The corresponding pin is implemented in this GPIO port. There is one PARAMETER register per GPIO port.
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UC3D 18.7.21 Name: Version Register VERSION Access Type: Read-only Offset: 0x1FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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UC3D 18.8 Module Configuration The specific configuration for each GPIO instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 18-3. Module Configuration Feature GPIO Number of GPIO ports 2 Number of peripheral functions 4 Table 18-4. Implemented Pin Functions Pin Function Implemented Notes Pull-up On all pins Controlled by PUER or peripheral Glitch Filter No Table 18-5.
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UC3D 19. USB Interface (USBC) Rev: 2.0.0.15 19.1 Features • • • • • • • 19.2 Compatible with the USB 2.0 specification Supports full (12Mbit/s) and low (1.
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UC3D • User interface • USB Core • Transceiver pads Figure 19-1. USBC Block Diagram USB HSB HSB Master USB_VBUS PB DM User interface USB 2.
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UC3D 19.4 I/O Lines Description Table 19-2.
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UC3D 19.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 19.5.1 I/O Lines The USBC pins may be multiplexed with the I/O Controller lines. The user must first configure the I/O Controller to assign the desired USBC pins to their peripheral functions. 19.5.
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UC3D 19.6 Functional Description 19.6.1 USB General Operation 19.6.1.1 Initialization After a hardware reset, the USBC is in the Reset state. In this state: • The module is disabled. The USBC Enable bit in the General Control register (USBCON.USBE) is reset. • The module clock is stopped in order to minimize power consumption. The Freeze USB Clock bit in USBCON (USBCON.FRZCLK) is set. • The USB pad is in suspend mode. • The internal states and registers of the device are reset.
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UC3D Figure 19-2. Speed Selection in device mode RPU VBUS UDCON.DETACH UDCON.LS DP DM 19.6.1.5 Data management Endpoints and pipe buffers can be allocated anywhere in the embedded memory (CPU RAM or HSB RAM). See ”RAM management” on page 292. 19.6.1.6 Pad Suspend Figure 19-3 illustrates the behavior of the USB pad in device mode. Figure 19-3. Pad Behavior Idle USBE = 0 | DETACH = 1 | Suspend USBE = 1 & DETACH = 0 & Suspend Active • In Idle state, the pad is in low power consumption mode.
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UC3D Figure 19-4. Pad events SUSP Suspend detected WAKEUP Cleared on Wakeup Wakeup detected Cleared by software to acknowledge the interrupt PAD state Active Idle Active The Suspend Interrupt bit in the Device Global Interrupt register (UDINT.SUSP) is set and the Wakeup Interrupt (UDINT.WAKEUP) bit is cleared when a USB Suspend state has been detected on the USB bus. This event automatically puts the USB pad in the Idle state.
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UC3D 19.6.2 USBC Device Mode Operation 19.6.2.1 Device Enabling In device mode, the USBC supports full- and low-speed data transfers. Including the default control endpoint, a total of None endpoints are provided. They can be configured as isochronous, bulk or interrupt types, as described in Table 19-1 on page 283 After a hardware reset, the USBC device mode is in the reset state (see Section 19.6.1.1). In this state, the endpoint banks are disabled and neither DP nor DM are pulled up (DETACH is one).
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UC3D • After all kinds of resets, the USB device address is 0. • The host starts a SETUP transaction with a SET_ADDRESS(addr) request. • The user writes this address to the USB Address field (UDCON.UADD), and writes a zero to the Address Enable bit (UDCON.ADDEN), resulting in the address remaining zero. • The user sends a zero-length IN packet from the control endpoint. • The user enables the stored USB device address by writing a one to ADDEN.
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UC3D • The user may then write a one to the remote wakeup (RMWKUP) bit in UDCON to send an Upstream Resume to the host initiating the wakeup. This will automatically be done by the controller after 5ms of inactivity on the USB bus. • When the controller sends the Upstream Resume, the Upstream Resume (UPRSM) interrupt is set and SUSP is cleared. • RMWKUP is cleared at the end of the transmitting Upstream Resume.
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UC3D Figure 19-5.
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UC3D • The control and status fields for the endpoint and bank (EPn_CTR_STA_BK0/1): Table 19-4. 31:19 EPn_CTR_STA_BK0/1 structure 18 17 16 15:1 Status elements - UNDERF OVERF 0 Control elements CRCERR - STALLRQ_NEXT – UNDERF: Underflow status for isochronous IN transfer. See ”Data flow error” on page 301. – OVERF: Overflow status for isochronous OUT transfer. See ”Data flow error” on page 301. – CRCERR: CRC error status for isochronous OUT transfer. See ”CRC error” on page 301.
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UC3D 19.6.2.12 Multi packet mode and single packet mode. Single packet mode is the default mode where one USB packet is managed per bank. The multi-packet mode allows the user to manage data exceeding the maximum endpoint size (UECFGn.EPSIZE) for an endpoint bank across multiple packets without software intervention. This mode can also be coupled with the ping-pong mode. • For an OUT endpoint, the EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE field should be configured correctly to enable the multi-packet mode.
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UC3D Figure 19-6. Control Write SETUP USB Bus RXSTPI DATA SETUP HW OUT STATUS OUT IN IN NAK SW RXOUTI HW SW HW SW TXINI SW • Control read Figure 19-7 on page 296 shows a control read transaction. The USBC has to manage the simultaneous write requests from the CPU and USB host. Figure 19-7.
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UC3D 19.6.2.14 Management of IN endpoints • Overview IN packets are sent by the USBC device controller upon IN requests from the host. The endpoint and its descriptor in RAM must be pre configured (see section ”RAM management” on page 292 for more details). When the current bank is clear, the TXINI and FIFO Control (UECONn.FIFOCON) bits will be set simultaneously. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.
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UC3D • Detailed description The data is written according to this sequence: • When the bank is empty, TXINI and FIFOCON are set, which triggers an EPnINT interrupt if TXINE is one. • The user acknowledges the interrupt by clearing TXINI. • The user reads the UESTAX.CURRBK field to see which the current bank is. • The user writes the data to the current bank, located in RAM as described by its descriptor: EPn_ADDR_BK0/1.
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UC3D set, or if the total byte count is not an integral multiple of EPSIZE, whereby the last packet should be short. To enable the multi packet mode, the user should configure the endpoint descriptor (EPn_PCKSIZE_BK0/1.BYTE_COUNT) to the total size of the multi packet, which should be larger than the endpoint size (EPSIZE). Since the EPn_PCKSIZE_BK0/1.
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UC3D Figure 19-12. Example of an OUT endpoint with two data banks OUT DATA (bank 0) ACK OUT DATA (bank 1) HW RXOUTI ACK HW SW SW read data from CPU BANK 0 FIFOCON SW read data from CPU BANK 1 • Detailed description Before using the OUT endpoint, one should properly initialize its descriptor for each bank. See Figure 19-5 on page 293. The data is read, according to this sequence: • When the bank is full, RXOUTI and FIFOCON are set, which triggers an EPnINT interrupt if RXOUTE is one.
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UC3D • A packet has been successfully received and the updated BYTE_COUNT equals the MULTI_PACKET_SIZE. • A short packet (smaller than EPSIZE) has been received. 19.6.2.16 Data flow error This error exists only for isochronous IN/OUT endpoints. It sets the Errorflow Interrupt (ERRORFI) bit in UESTAn, which triggers an EPnINT interrupt if the Errorflow Interrupt Enable (ERRORFE) bit is one. The user can check the EPn_CTR_STA_BK0/1.
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UC3D • The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one) • Endpoint interrupts The processing device endpoint interrupts are: • The Transmitted IN Data Interrupt (TXINI) • The Received OUT Data Interrupt (RXOUTI) • The Received SETUP Interrupt (RXSTPI) • The Number of Busy Banks (NBUSYBK) interrupt The exception device endpoint interrupts are: • The Errorflow Interrupt (ERRORFI) • The NAKed OUT Interrupt (NAKOUTI) • The NAKed IN Interrupt (NAKINI) • The STALLed Interrupt (STAL
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UC3D 19.7 User Interface Table 19-5.
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UC3D 19.7.1 USB General Registers 19.7.1.1 Name: General Control Register USBCON Access Type: Read/Write Offset: 0x0800 Reset Value: 0x00004000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 11 10 9 8 USBE FRZCLK - - - - - - 7 6 5 4 3 2 1 0 - - - - - - VBUSTE - - - • USBE: USBC Enable Writing a zero to this bit will disable the USBC, USB transceiver, and USB clock inputs.
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UC3D 19.7.1.2 General Status Register Register Name: USBSTA Access Type: Read-Only Offset: 0x0804 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CLKUSABLE VBUS - - - 7 6 5 4 3 2 1 0 - - - - - - VBUSTI - SPEED • CLKUSABLE: Generic Clock Usable This bit is cleared when the USB generic clock is not usable.
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UC3D 19.7.1.3 General Status Clear Register Register Name: USBSTACLR Access Type: Write-Only Offset: 0x0808 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - VBUSTIC - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in USBSTA.
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UC3D 19.7.1.4 General Status Set Register Register Name: USBSTASET Access Type: Write-Only Offset: 0x080C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - VBUSTIS - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in USBSTA.
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UC3D 19.7.1.5 Version Register Register Name: UVERS Access Type: Read-Only Offset: 0x0818 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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UC3D 19.7.1.
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UC3D 19.7.1.7 Address Size Register Register Name: UADDRSIZE Access Type: Read-Only Offset: 0x0820 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UADDRSIZE[31:24] 23 22 21 20 19 UADDRSIZE[23:16] 15 14 13 12 11 UADDRSIZE[15:8] 7 6 5 4 3 UADDRSIZE[7:0] • UADDRSIZE: IP PB Address Size This field indicates the size of the PB address space reserved for the USBC IP interface.
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UC3D 19.7.1.8 IP Name Register 1 Register Name: UNAME1 Access Type: Read-Only Offset: 0x0824 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME1[31:24] 23 22 21 20 19 UNAME1[23:16] 15 14 13 12 11 UNAME1[15:8] 7 6 5 4 3 UNAME1[7:0] • UNAME1: IP Name Part One This field indicates the first part of the ASCII-encoded name of the USBC IP.
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UC3D 19.7.1.9 IP Name Register 2 Register Name: UNAME2 Access Type: Read-Only Offset: 0x0828 Reset Value: 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME2[31:24] 23 22 21 20 19 UNAME2[23:16] 15 14 13 12 11 UNAME2[15:8] 7 6 5 4 3 UNAME2[7:0] • UNAME2: IP Name Part Two This field indicates the second part of the ASCII-encoded name of the USBC IP.
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UC3D 19.7.1.10 Finite State Machine Status Register Register Name: USBFSM Access Type: Read-Only Offset: 0x082C Reset Value: 0x00000009 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - DRDSTATE • DRDSTATE: Dual Role Device State This field indicates the state of the USBC. For Device mode it should always read 9.
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UC3D 19.7.1.11 USB Descriptor Address Register Name: UDESC Access Type: Read-Write Offset: 0x0830 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UDESCA[31:24] 23 22 21 20 19 UDESCA[23:16] 15 14 13 12 11 UDESCA[15:8] 7 6 5 4 3 UDESCA[7:0] • UDESCA: USB Descriptor Address This field contains the address of the USB descriptor. The three least significant bits are always zero.
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UC3D 19.7.2 USB Device Registers 19.7.2.1 Device General Control Register Register Name: UDCON Access Type: Read/Write Offset: 0x0000 Reset Value: 0x00000100 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - GNAK - 15 14 13 12 11 10 9 8 - - - LS - - RMWKUP DETACH 7 6 5 4 3 2 1 0 ADDEN UADD • GNAK: Global NAK 0: Normal mode.
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UC3D 19.7.2.2 Device Global Interrupt Register Register Name: UDINT Access Type: Read-Only Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 18 (1) EP7INT EP6INT 17 (1) EP5INT 16 (1) EP4INT(1) - - - 15 14 13 12 11 10 9 8 EP3INT(1) EP2INT(1) EP1INT(1) EP0INT - - - - 7 6 5 4 3 2 1 0 - UPRSM EORSM WAKEUP EORST SOF - SUSP Note: EP8INT 19 (1) 1. EPnINT bits are within the range from EP0INT to EP6INT.
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UC3D • SUSP: Suspend Interrupt This bit is cleared when the UDINTCLR.SUSPC bit is written to one to acknowledge the interrupt or when the Wakeup (WAKEUP) interrupt bit is set. This bit is set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a USB interrupt if SUSPE is one.
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UC3D 19.7.2.3 Device Global Interrupt Clear Register Register Name: UDINTCLR Access Type: Write-Only Offset: 0x0008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UPRSMC EORSMC WAKEUPC EORSTC SOFC - SUSPC Writing a zero to a bit in this register has no effect.
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UC3D 19.7.2.4 Device Global Interrupt Set Register Register Name: UDINTSET Access Type: Write-Only Offset: 0x000C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UPRSMS EORSMS WAKEUPS EORSTS SOFS - SUSPS Writing a zero to a bit in this register has no effect.
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UC3D 19.7.2.5 Device Global Interrupt Enable Register Register Name: UDINTE Access Type: Read-Only Offset: 0x0010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 (1) EP7INTE 17 (1) EP6INTE 16 (1) EP5INTE EP4INTE(1) - - - 15 14 13 12 11 10 9 8 EP3INTE(1) EP2INTE(1) EP1INTE(1) EP0INTE - - - - 7 6 5 4 3 2 1 0 - UPRSME EORSME WAKEUPE EORSTE SOFE - SUSPE Note: EP8INTE 18 (1) 1.
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UC3D 19.7.2.6 Device Global Interrupt Enable Clear Register Register Name: UDINTECLR Access Type: Write-Only Offset: 0x0014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 (1) EP7INTEC 17 (1) EP6INTEC EP5INTEC 16 (1) EP4INTEC(1) - - - 15 14 13 12 11 10 9 8 EP3INTEC(1) EP2INTEC(1) EP1INTEC(1) EP0INTEC - - - - 7 6 5 4 3 2 1 0 - UPRSMEC EORSMEC WAKEUPEC EORSTEC SOFEC - SUSPEC Note: EP8INTEC 18 (1) 1.
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UC3D 19.7.2.7 Device Global Interrupt Enable Set Register Register Name: UDINTESET Access Type: Write-Only Offset: 0x0018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 (1) EP7INTES 17 (1) EP6INTES 16 (1) EP5INTES EP4INTES(1) - - - 15 14 13 12 11 10 9 8 EP3INTES(1) EP2INTES(1) EP1INTES(1) EP0INTES - - - - 7 6 5 4 3 2 1 0 - UPRSMES EORSMES WAKEUPES EORSTES SOFES - SUSPES Note: EP8INTES 18 (1) 1.
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UC3D 19.7.2.8 Endpoint Enable/Reset Register Register Name: UERST Access Type: Read/Write Offset: 0x001C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - EPEN8(1) 7 6 5 4 3 2 1 0 EPEN7(1) EPEN6(1) EPEN5(1) EPEN4(1) EPEN3(1) EPEN2(1) EPEN1(1) EPEN0 • EPENn: Endpoint n Enable Note: 1. EPENn bits are within the range from EPEN0 to EPEN6.
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UC3D 19.7.2.9 Device Frame Number Register Register Name: UDFNUM Access Type: Read-Only Offset: 0x0020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 FNCERR - 7 6 2 1 0 - - - FNUM[10:5] 5 FNUM[4:0] 4 3 • FNCERR: Frame Number CRC Error This bit is cleared upon receiving a USB reset. This bit is set when a corrupted frame number is received.
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UC3D 19.7.2.10 Endpoint n Configuration Register Register Name: UECFGn, n in [0..
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UC3D EPSIZE Endpoint Size 1 0 1 256 bytes 1 1 0 512 bytes 1 1 1 1024 bytes This field is cleared upon receiving a USB reset (except for the endpoint 0). • EPBK: Endpoint Banks This bit selects the number of banks for the endpoint: 0: single-bank endpoint 1: double-bank endpoint For control endpoints, a single-bank endpoint shall be selected. This field is cleared upon receiving a USB reset (except for the endpoint 0).
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UC3D 19.7.2.11 Endpoint n Status Register Register Name: UESTAn, n in [0..
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UC3D For IN endpoints, this indicates the number of banks filled by the user and ready for IN transfers. When all banks are free an EPnINT interrupt will be triggered if NBUSYBKE is one. For OUT endpoints, this indicates the number of banks filled by OUT transactions from the host. When all banks are busy an EPnINT interrupt will be triggered if NBUSYBKE is one. • RAMACERI: Ram Access Error Interrupt This bit is cleared when the RAMACERIC bit is written to one, acknowledging the interrupt.
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UC3D This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPnINT interrupt if RXOUTE is one. This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full. This triggers an EPnINT interrupt if RXOUTE is one. This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
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UC3D 19.7.2.12 Endpoint n Status Clear Register Register Name: UESTAnCLR, n in [0..6] Access Type: Write-Only Offset: 0x0160 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - RAMACERIC - - - 7 6 5 4 3 2 1 0 - STALLEDIC/ CRCERRIC - NAKINIC NAKOUTIC RXSTPIC/ ERRORFIC RXOUTIC TXINIC Writing a zero to a bit in this register has no effect.
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UC3D 19.7.2.13 Endpoint n Status Set Register Register Name: UESTAnSET, n in [0..6] Access Type: Write-Only Offset: 0x0190 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - NBUSYBKS RAMACERIS - 7 6 5 4 3 2 1 0 - STALLEDIS/ CRCERRIS - NAKINIS NAKOUTIS RXSTPIS/ ERRORFIS RXOUTIS TXINIS - Writing a zero to a bit in this register has no effect.
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UC3D 19.7.2.14 Endpoint n Control Register Register Name: UECONn, n in [0..
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UC3D • KILLBK: Kill IN Bank • • • • • • • • • • This bit is cleared by hardware after the completion of the “kill packet procedure”. This bit is set when the KILLBKS bit is written to one, killing the last written bank. The user shall wait for this bit to be cleared before trying to process another IN packet. Caution: The bank is cleared when the “kill packet” procedure is completed by the USBC core: If the bank is really killed, the NBUSYBK field is decremented.
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UC3D 19.7.2.15 Endpoint n Control Clear Register Register Name: UECONnCLR, n in [0..
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UC3D 19.7.2.16 Endpoint n Control Set Register Register Name: UECONnSET, n in [0..
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UC3D 19.8 Module Configuration Table 19-6. USBC Clocks Clock Name Description CLK_USBC Clock for the USBC bus interface GCLK_USBC 48Mhz USB clock. This clock frequency must be configured to 48MHz. The generic clock used for the USBC is GCLK3 Table 19-7.
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UC3D 20. Universal Synchronous Asynchronous Receiver Transmitter (USART) Rev: 4.4.0.6 20.1 Features • Configurable baud rate generator • 5- to 9-bit full-duplex, synchronous and asynchronous, serial communication – 1, 1.
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UC3D 20.3 Block Diagram Figure 20-1. USART Block Diagram Peripheral DMA Controller Channel Channel USART I/O Controller RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS CLK_USART Power Manager DIV BaudRate Generator CLK_USART/DIV CLK User Interface Peripheral bus Table 20-1.
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UC3D 20.4 I/O Lines Description Table 20-2.
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UC3D 20.6 Functional Description 20.6.1 Baud Rate Generator The baud rate generator provides the bit period clock named the Baud Rate Clock to both receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator, and if CD is one, the divider is bypassed and inactive. The Clock Selection field in the Mode Register (MR.
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UC3D Table 20-3. Baud Rate Example (OVER=0) Source Clock (Hz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.
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UC3D 20.6.2 Receiver and Transmitter Control After a reset, the transceiver is disabled. The receiver/transmitter is enabled by writing a one to either the Receiver Enable, or Transmitter Enable bit in the Control Register (CR.RXEN, or CR.TXEN). They may be enabled together and can be configured both before and after they have been enabled. The user can reset the USART receiver/transmitter at any time by writing a one to either the Reset Receiver (CR.RSTRX), or Reset Transmitter (CR.RSTTX) bit.
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UC3D Figure 20-4. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY 20.6.3.2 Asynchronous Receiver If the USART is configured in an asynchronous operating mode (MR.SYNC = 0), the receiver will oversample the RXD input line by either 8 or 16 times the baud rate clock, as selected by the Oversampling Mode bit (MR.OVER).
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UC3D Figure 20-6. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 20.6.3.3 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Synchronous Receiver In synchronous mode (SYNC=1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start bit.
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UC3D Figure 20-8. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write CR Read RHR RXRDY OVRE 20.6.3.5 Parity The USART supports five parity modes selected by MR.PAR. The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page 346.
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UC3D 20.6.3.6 Multidrop Mode If PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data and address characters. Data has the parity bit zero and addresses have a one. By writing a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR to be transmitted as an address. Receiving a character with a one as parity bit will set PARE. 20.6.3.
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UC3D TO is loaded to a decremental counter, and unless it is zero, a time-out will occur when the amount of inactive bit periods match the initial counter value. If a time-out has not occurred, the counter will reload and restart every time a new character arrives. A time-out sets the TIMEOUT bit in CSR. Clearing TIMEOUT can be done in two ways: • Writing a one to the Start Time-out bit (CR.STTTO). This also aborts count down until the next character has been received.
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UC3D Figure 20-12. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write CR FRAME RXRDY 20.6.3.10 Transmit Break When TXRDY is set, the user can request the transmitter to generate a break condition on the TXD line by writing a one to The Start Break bit (CR.STTBRK). The break is treated as a normal 0x00 character transmission, clearing TXRDY and TXEMPTY, but with zeroes for preambles, start, parity, stop, and time guard bits.
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UC3D 20.6.3.12 Hardware Handshaking The USART features an out-of-band hardware handshaking flow control mechanism, implementable by connecting the RTS and CTS pins with the remote device, as shown in Figure 2014. Figure 20-14. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Writing 0x2 to the MR.MODE field configures the USART to operate in this mode.
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UC3D 20.6.4 SPI Mode The USART features a Serial Peripheral Interface (SPI) link compliant mode, supporting synchronous, full-duplex communication, in both master and slave mode. Writing 0xE (master) or 0xF (slave) to MR.MODE will enable this mode. A SPI in master mode controls the data flow to and from the other SPI devices, who are in slave mode.
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UC3D Table 20-7. SPI Bus Protocol Modes SPI Bus Protocol Mode CPOL CPHA 0 0 1 1 0 0 2 1 1 3 1 0 Figure 20-18.
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UC3D Figure 20-19. SPI Transfer Format (CPHA=0, 8 bits per transfer) CLK cycle (for reference) 1 2 3 4 5 6 7 8 CLK (CPOL= 0) CLK (CPOL= 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 20.6.4.4 Receiver and Transmitter Control See ”Transmitter Operations” on page 342, and ”Receiver Operations” on page 344. 20.6.4.
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UC3D 20.6.5 20.6.6 Test Modes The internal loopback feature enables on-board diagnostics, and allows the USART to operate in three different test modes, with reconfigured pin functionality, as shown below. 20.6.6.1 Normal Mode During normal operation, a receivers RXD pin is connected to a transmitters TXD pin. Figure 20-20. Normal Mode Configuration RXD Receiver TXD Transmitter 20.6.6.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission.
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UC3D Figure 20-23. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 20.6.7 Write Protection Registers To prevent single software errors from corrupting USART behavior, certain address spaces can be write-protected by writing the correct Write Protect KEY and a one to the Write Protect Enable bit in the Write Protect Mode Register (WPMR.WPKEY, and WPMR.WPEN). Disabling the write protection is done by writing the correct key, and a zero to WPEN.
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UC3D 20.7 User Interface Table 20-8.
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UC3D 20.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x0 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS/RCS 18 RTSEN/FCS 17 – 16 – 15 RETTO 14 RSTNACK 13 – 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select Writing a zero to this bit has no effect.
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UC3D • STTBRK: Start Break Writing a zero to this bit has no effect. Writing a one to this bit will start transmission of break characters when current characters present in THR and the transmit shift register have been sent. No effect if a break signal is already being generated. • RSTSTA: Reset Status Bits Writing a zero to this bit has no effect. Writing a one to this bit will clear the following bits in CSR: PARE, FRAME, OVRE, and RXBRK.
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UC3D 20.7.2 Name: Mode Register MR Access Type: Read-write Offset: 0x4 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 25 – 24 23 – 22 – 21 – 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF/CPOL 14 13 12 11 10 PAR 9 8 SYNC/CPHA 4 3 2 1 0 15 CHMODE 7 NBSTOP 6 CHRL 5 USCLKS MODE This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated.
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UC3D • CHMODE: Channel Mode Table 20-9. CHMODE Mode Description 0 0 Normal Mode 0 1 Automatic Echo. Receiver input is connected to the TXD pin. 1 0 Local Loopback. Transmitter output is connected to the Receiver input. 1 1 Remote Loopback. RXD pin is internally connected to the TXD pin. • NBSTOP: Number of Stop Bits Table 20-10. NBSTOP Asynchronous (SYNC=0) Synchronous (SYNC=1) 0 0 1 stop bit 1 stop bit 0 1 1.
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UC3D • CHRL: Character Length. Table 20-12. CHRL Character Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits • USCLKS: Clock Selection Table 20-13. USCLKS Note: Selected Clock 0 0 CLK_USART 0 1 CLK_USART/DIV(1) 1 0 Reserved 1 1 CLK 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the end of this chapter. • MODE Table 20-14.
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UC3D 20.7.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x8 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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UC3D 20.7.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0xC Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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UC3D 20.7.5 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 20.7.6 Name: Channel Status Register CSR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY • CTS: Image of CTS Input 0: CTS is low. 1: CTS is high.
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UC3D • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break received or End of Break detected since the last RSTSTA. • TXRDY: Transmitter Ready 0: The transmitter is either disabled, or a character in THR is waiting to be transferred to the transmit shift register, or an STTBRK command has been requested.
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UC3D 20.7.7 Name: Receiver Holding Register RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR[8] 7 6 5 4 3 2 1 0 RXCHR[7:0] • RXCHR: Received Character Last received character.
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UC3D 20.7.8 Name: Transmitter Holding Register THR Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR[8] 7 6 5 4 3 2 1 0 TXCHR[7:0] • TXCHR: Character to be Transmitted If TXRDY is zero this field contains the next character to be transmitted.
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UC3D 20.7.9 Name: Baud Rate Generator Register BRGR Access Type: Read-write Offset: 0x20 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 – 16 15 14 13 12 11 10 9 8 3 2 1 0 CD[15:8] 7 6 5 4 CD[7:0] This register can only be written to if write protection is disabled, see ”Write Protect Mode Register” on page 371. • CD: Clock Divider Table 20-15.
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UC3D 20.7.10 Name: Receiver Time-out Register RTOR Access Type: Read-write Offset: 0x24 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO[15:8] 7 6 5 4 TO[7:0] This register can only be written to if write protection is disabled, see ”Write Protect Mode Register” on page 371. • TO: Time-out Value 0: The receiver Time-out is disabled.
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UC3D 20.7.11 Name: Transmitter Timeguard Register TTGR Access Type: Read-write Offset: 0x28 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written to if write protection is disabled, see ”Write Protect Mode Register” on page 371. • TG: Timeguard Value 0: The transmitter Timeguard is disabled.
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UC3D 20.7.12 Write Protect Mode Register Register Name: WPMR Access Type: Read-write Offset: 0xE4 Reset Value: See Table 20-8 31 30 29 28 27 WPKEY[23:16] 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY[15:8] 15 14 13 12 WPKEY[7:0] 7 — 6 — 5 — 4 — • WPKEY: Write Protect KEY Has to be written to 0x555341 (“USA” in ASCII) in order to successfully write WPEN. Always reads as zero. • WPEN: Write Protect Enable 0 = Write protection disabled.
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UC3D 20.7.13 Write Protect Status Register Register Name: WPSR Access Type: Read-only Offset: 0xE8 Reset Value: See Table 20-8 31 — 30 — 29 — 28 — 27 — 26 — 25 — 24 — 23 22 21 20 19 WPVSRC[15:8] 18 17 16 15 14 13 12 11 10 9 8 3 — 2 — 1 — 0 WPVS WPVSRC[7:0] 7 — 6 — 5 — 4 — • WPVSRC: Write Protect Violation Source If WPVS=1 this field indicates which write-protected register was unsuccessfully written to, either by address offset or code.
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UC3D 20.7.14 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 18 17 16 15 – 14 – 13 – 12 – 11 10 9 VERSION[11:8] 8 7 6 5 4 3 2 0 MFN 1 VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version of the module. No functionality associated.
PAGE 374
UC3D 20.8 Module Configuration The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 20-16.
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UC3D 21. Serial Peripheral Interface (SPI) Rev: 2.1.1.3 21.
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UC3D 21.3 Block Diagram Figure 21-1. SPI Block Diagram Peripheral DMA Controller Peripheral Bus SPCK MISO CLK_SPI MOSI Spi Interface I/O Controller NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 21.4 Application Block Diagram Figure 21-2.
PAGE 377
UC3D 21.5 I/O Lines Description Table 21-1. I/O Lines Description Type 21.6 Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 21.6.
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UC3D 21.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two bits determine the edges of the clock signal on which data is driven and sampled. Each of the two bits has two possible states, resulting in four possible combinations that are incompatible with one another.
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UC3D Figure 21-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) *** MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) *** Not Defined, but normaly LSB of previous character transmitted 21.7.3 Master Mode Operations When configured in master mode, the SPI uses the internal programmable baud rate generator as clock source.
PAGE 380
UC3D Figure 21-5 on page 380shows a block diagram of the SPI when operating in master mode. Figure 21-6 on page 381 shows a flow chart describing how transfers are handled. 21.7.3.1 Master mode block diagram Figure 21-5. Master Mode Block Diagram CSR0..3 SCBR CLK_SPI Baud Rate Generator SPCK SPI Clock RXFIFOEN RDR RDRF OVRES RD CSR0..3 LSB MISO BITS NCPHA 0 CPOL 1 4 – Character FIFO MSB Shift Register MOSI TDR TD TDRE RXFIFOEN RDR CSR0..
PAGE 381
UC3D 21.7.3.2 Master mode flow diagram Figure 21-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
PAGE 382
UC3D 21.7.3.3 Clock generation The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255. Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbidden. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results. At reset, CSRn.
PAGE 383
UC3D 21.7.3.5 Peripheral selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: • Fixed Peripheral Select: SPI exchanges data with only one peripheral • Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing a zero to the Peripheral Select bit in MR (MR.
PAGE 384
UC3D to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. When the CSRn.
PAGE 385
UC3D Figure 21-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..3] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B B A DLYBCS DLYBCS PCS = B PCS = B Write TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE NPCS[0..
PAGE 386
UC3D register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a low level is driven by an external master on the NPCS0/NSS signal. When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable bit in the CR register (CR.SPIEN). By default, the mode fault detection circuitry is enabled.
PAGE 387
UC3D Figure 21-9.
PAGE 388
UC3D 21.8 User Interface Table 21-3.
PAGE 389
UC3D 21.8.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - FLUSHFIFO 7 6 5 4 3 2 1 0 SWRST - - - - - SPIDIS SPIEN • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
PAGE 390
UC3D 21.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 DLYBCS 23 22 21 20 - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 LLB RXFIFOEN - MODFDIS - PCSDEC PS MSTR PCS • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
PAGE 391
UC3D 0: The FIFO is not used in reception (only one character can be stored in the SPI). • MODFDIS: Mode Fault Detection 1: Mode fault detection is disabled. If the I/O controller does not have open-drain capability, mode fault detection must be disabled for proper operation of the SPI. 0: Mode fault detection is enabled. • PCSDEC: Chip Select Decode 0: The chip selects are directly connected to a peripheral device. 1: The four chip select lines are connected to a 4- to 16-bit decoder.
PAGE 392
UC3D 21.8.3 Name: Receive Data Register RDR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RD[15:8] 7 6 5 4 RD[7:0] • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
PAGE 393
UC3D 21.8.4 Name: Transmit Data Register TDR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD[15:8] 7 6 5 4 TD[7:0] • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
PAGE 394
UC3D 21.8.5 Name: Status Register SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - SPIENS 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF • SPIENS: SPI Enable Status 1: This bit is set when the SPI is enabled. 0: This bit is cleared when the SPI is disabled.
PAGE 395
UC3D 21.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 396
UC3D 21.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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UC3D 21.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 21.8.9 Name: Chip Select Register 0 CSR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
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UC3D • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
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UC3D CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 401
UC3D 21.8.10 Name: Chip Select Register 1 CSR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
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UC3D • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
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UC3D CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 404
UC3D 21.8.11 Name: Chip Select Register 2 CSR2 Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
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UC3D • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
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UC3D CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 407
UC3D 21.8.12 Name: Chip Select Register 3 CSR3 Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
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UC3D • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
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UC3D CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 410
UC3D 21.8.13 Write Protection Control Register Register Name: WPCR Access Type: Read-write Offset: 0xE4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 10 9 8 SPIWPKEY[23:16] 23 22 21 20 19 SPIWPKEY[15:8] 15 14 13 12 11 SPIWPKEY[7:0] 7 6 5 4 3 2 1 0 - - - - - - - SPIWPEN • SPIWPKEY: SPI Write Protection Key Password If a value is written in SPIWPEN, the value is taken into account only if SPIWPKEY is written with “SPI” (SPI written in ASCII Code, i.e.
PAGE 411
UC3D 21.8.
PAGE 412
UC3D 21.8.15 Features Register Register Name: FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - SWIMPL FIFORIMPL BRPBHSB CSNAATIMPL EXTDEC 15 14 13 12 11 10 9 8 LENNCONF 7 6 5 4 PHZNCONF PHCONF PPNCONF PCONF LENCONF 3 2 1 0 NCS • SWIMPL: Spurious Write Protection Implemented • • • • • • • • 0: Spurious write protection is not implemented.
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UC3D • PPNCONF: Polarity Positive if Polarity not Configurable 0: If polarity is not configurable, polarity is negative. 1: If polarity is not configurable, polarity is positive. • PCONF: Polarity Configurable 0: Polarity is not configurable. 1: Polarity is configurable. • NCS: Number of Chip Selects This field indicates the number of chip selects implemented.
PAGE 414
UC3D 21.8.16 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 MFN 11 10 VERSION[11:8] 7 6 5 4 3 2 1 0 VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version number of the module. No functionality associated.
PAGE 415
UC3D 21.9 Module Configuration The specific configuration for each SPI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 21-4. SPI Clock Name Module Name Clock Name SPI CLK_SPI Table 21-5.
PAGE 416
UC3D 22. Inter-IC Sound Controller (IISC) Rev: 1.0.0.0 22.1 Features • Compliant with Inter-IC Sound (I2S) bus specification • Master, slave, and controller modes: • • • • • 22.
PAGE 417
UC3D 22.3 Block Diagram Figure 22-1. IISC Block Diagram IISC Peripheral DMA Controller Interrupt Controller 22.4 Clocks PB clock PB Rx Tx IRQ Transmitter IWS ISDI ISDO I/O Lines Description Table 22-1. I/O Lines Description Pin Name 22.
PAGE 418
UC3D 22.5.3 Clocks The clock for the IISC bus interface (CLK_IISC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the IISC before disabling the clock, to avoid freezing the IISC in an undefined state. One of the generic clocks is connected to the IISC. The generic clock (GCLK_IISC) can be set to a wide range of frequencies and clock sources. The GCLK_IISC must be enabled and configured before use.
PAGE 419
UC3D The Transmitter can be operated by writing to the Transmitter Holding Register (RHR), whenever the Transmit Ready (TXRDY) bit in the Status Register (SR) is set. Successive values written to THR should correspond to the samples from the left and right audio channels for the successive frames. The Receive Ready and Transmit Ready bits can be polled by reading the Status Register. The IISC processor load can be reduced by enabling interrupt-driven operation.
PAGE 420
UC3D 22.6.5 Serial Clock and Word Select Generation The generation of clocks in the IISC is described in Figure 22-3 on page 421. In Slave mode, the Serial Clock and Word Select Clock are driven by an external master. ISCK and IWS pins are inputs and no generic clock is required by the IISC. In Master mode, the user can configure the Master Clock, Serial Clock, and Word Select Clock through the Mode Register (MR). IMCK, ISCK, and IWS pins are outputs and a generic clock is used to derive the IISC clocks.
PAGE 421
UC3D Figure 22-3. IISC Clocks Generation CR.CKEN/CKDIS MR.IMCKMODE Clock enable GCLK_IISC IMCK pin output Clock divider MR.IMCKMODE 0 MR.IMCKFS MR.DATALENGTH 1 ISCK pin output CR.CKEN/CKDIS 0 ISCK pin input 1 Internal bit clock Clock enable Clock divider MR.MODE = SLAVE MR.DATALENGTH IWS pin output 0 IWS pin input 22.6.6 1 Internal word clock Mono When the Transmit Mono (TXMONO) in the Mode Register is set, data written to the left channel is duplicated to the right output channel.
PAGE 422
UC3D Data words are right-justified in the RHR and THR registers. For 16-bit compact stereo, the left sample uses bits 15 through 0 and the right sample uses bits 31 through 16 of the same data word. For 8-bit compact stereo, the left sample uses bits 7 through 0 and the right sample uses bits 15 through 8 of the same data word. 22.6.8 DMA Operation The Receiver and the Transmitter can each be connected either to one single Peripheral DMA channel or to one Peripheral DMA channel per data channel.
PAGE 423
UC3D Figure 22-4. Interrupt Block Diagram IER Set IMR Clear IDR Transmitter TXRDY TXUR Interrupt Control IISC Interrupt Request Receiver RXRDY RXOR 22.7 IISC Application Examples The IISC can support several serial communication modes used in audio or high-speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the IISC are not listed here. Figure 22-5.
PAGE 424
UC3D Figure 22-6. Codec Application Block Diagram IMCK ISCK IISC IWS ISDO ISDI Master Clock Serial Clock EXTERNAL AUDIO CODEC Word Select Serial Data Out Serial Data In Serial Clock Word Select Left Time Slot Right Time Slot Dstart Dend Serial Data Out Serial Data In Figure 22-7.
PAGE 425
UC3D 22.8 User Interface Table 22-3.
PAGE 426
UC3D 22.8.
PAGE 427
UC3D 22.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 IWS24 IMCKMODE 23 22 21 20 - - - 15 14 - 27 26 25 24 19 18 17 16 - - - - - 13 12 11 10 9 8 TXSAME TXDMA TXMONO RXLOOP RXDMA RXMONO 7 6 5 4 2 1 0 - - - - MODE IMCKFS 3 DATALENGTH The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs.
PAGE 428
UC3D Table 22-4.
PAGE 429
UC3D 22.8.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY TXEN - RXOR RXRDY RXEN TXURCH RXORCH • TXURCH: Transmit Underrun Channel This field is cleared when SCR.
PAGE 430
UC3D 22.8.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - TXURCH RXORCH Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.
PAGE 431
UC3D 22.8.5 Name: Status Set Register SSR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - TXURCH RXORCH Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in SR.
PAGE 432
UC3D 22.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 433
UC3D 22.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 434
UC3D 22.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 435
UC3D 22.8.9 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RHR[31:24] 23 22 21 20 RHR[23:16] 15 14 13 12 RHR[15:8] 7 6 5 4 RHR[7:0] • RHR: Received Word This field is set by hardware to the last received data word. If MR.DATALENGTH specifies less than 32 bits, data shall be rightjustified into the RHR field.
PAGE 436
UC3D 22.8.10 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 THR[31:24] 23 22 21 20 THR[23:16] 15 14 13 12 THR[15:8] 7 6 5 4 THR[7:0] • THR: Data Word to Be Transmitted Next data word to be transmitted after the current word if TXRDY is not set. If MR.DATALENGTH specifies less than 32 bits, data shall be right-justified into the THR field.
PAGE 437
UC3D 22.8.11 Name: Module Version VERSION Access Type: Read-only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 438
UC3D 22.8.12 Name: Module Parameters PARAMETER Access Type: Read-only Offset: 0x2C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - Reserved. No functionality associated.
PAGE 439
UC3D 22.9 Module configuration The specific configuration for each IISC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 22-7. IISC Clocks Clock Name Description CLK_IISC Clock for the IISC bus interface GCLK_IISC IISC output clock source. The generic clock used for the IISC is GCLK5 Table 22-8.
PAGE 440
UC3D 23. Two-wire Master Interface (TWIM) Rev.: 1.1.0.1 23.1 Features • Compatible with I²C standard • • • • • • 23.
PAGE 441
UC3D Table 23-2 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus compatible master. Table 23-2. 23.3 SMBus Standard Atmel TWIM Bus Timeouts Supported Address Resolution Protocol Supported Host Functionality Supported Packet Error Checking Supported List of Abbreviations Table 23-3. 23.
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UC3D 23.5 Application Block Diagram Figure 23-2. Application Block Diagram VDD Rp Rp Rp TWD TWI Master TWCK TWALM Atmel TWI serial EEPROM I2C RTC I2C LCD controller I2C temp sensor Slave 1 Slave 2 Slave 3 Slave 4 Rp: pull-up value as given by the I2C Standard 23.6 I/O Lines Description Table 23-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 23.
PAGE 443
UC3D 23.7.3 Clocks The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state. 23.7.4 DMA The TWIM DMA handshake interface is connected to the Peripheral DMA Controller. Using the TWIM DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIM. 23.7.
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UC3D 23.8 23.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 23-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 23-4). • A high-to-low transition on the TWD line while TWCK is high defines the START condition.
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UC3D 23.8.2.1 Clock Generation The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be selected through the Clock Prescaler field in CWGR (CWGR.EXP). f CLK_TWIM f PRESCALER = ------------------------( EXP + 1 ) 2 CWGR has the following fields: LOW: Prescaled clock cycles in clock low count.
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UC3D 23.8.2.2 Setting up and Performing a Transfer Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Register (CMDR). TWIM status is provided in the Status Register (SR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by writing to the Clock Waveform Generator Register (CWGR). If operating in SMBus mode, the SMBus Timing Register (SMBTR) register must also be configured. 2.
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UC3D TWI transfers require the slave to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not acknowledge the data byte.
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UC3D 1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state of RHR. Software or the Peripheral DMA Controller must read any data byte present in RHR. 2. Release TWCK generating a clock that the slave uses to transmit a data byte. 3. Place the received data byte in RHR, set RXRDY. 4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK. 5. Decrement NBYTES 6. If (NBYTES==0) and STOP=1, transmit STOP condition.
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UC3D 23.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space to place received data. To assure correct behavior, respect the following programming sequences: 23.8.5.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2.
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UC3D Figure 23-10. User Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 23-11.
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UC3D As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when data to transmit can be written to THR, or when received data can be read from RHR. Transfer of data to THR and from RHR can also be done automatically by DMA, see Section 23.8.5 23.8.7.1 Write Followed by Write Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP. To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2.
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UC3D Figure 23-12. Combining a Write and Read Transfer THR DATA0 DATA1 RHR TWD DATA2 S DADR W A DATA0 A DATA1 NA Sr R DADR A DATA2 A DATA3 DATA3 A P SR.IDLE 1 TXRDY RXRDY To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 5.
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UC3D 23.8.8 Ten Bit Addressing Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of CMDR.SADR must be written appropriately. In Figure 23-14 and Figure 23-15, the grey boxes represent signals driven by the master, the white boxes are driven by the slave. 23.8.8.1 Master Transmitter To perform a master transmitter transfer: 1.
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UC3D 23.8.9.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to CMDR.PECEN enables automatic PEC handling in the current transfer. Transfers with and without PEC can freely be intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on combined transfers will be correct.
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UC3D 23.8.10 Identifying Bus Events This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is intended to help writing drivers for the TWIM. Table 23-5. Bus Events Event Effect Master transmitter has sent a data byte SR.THR is cleared. Master receiver has received a data byte SR.RHR is set. Start+Sadr sent, no ack received from slave SR.ANAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus.
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UC3D 23.9 User Interface Table 23-6.
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UC3D 23.9.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - STOP 7 6 5 4 3 2 1 0 SWRST - SMDIS SMEN - - MDIS MEN • STOP: Stop the Current Transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle.
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UC3D 23.9.2 Name: Clock Waveform Generator Register CWGR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 - 23 29 28 27 26 EXP 22 21 25 24 DATA 20 19 18 17 16 11 10 9 8 3 2 1 0 STASTO 15 14 13 12 HIGH 7 6 5 4 LOW • EXP: Clock Prescaler Used to specify how to prescale the TWCK clock.
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UC3D 23.9.3 Name: SMBus Timing Register SMBTR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 THMAX 15 14 13 12 TLOWM 7 6 5 4 TLOWS • EXP: SMBus Timeout Clock Prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR.
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UC3D 23.9.4 Name: Command Register CMDR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 - 23 29 28 - 22 21 20 27 26 25 24 - - ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ • ACKLAST: ACK Last Master RX Byte 0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed.
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UC3D Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. Write this bit to zero otherwise. • TENBIT: Ten Bit Addressing Mode 0: Use 7-bit addressing mode. 1: Use 10-bit addressing mode. Must not be used when the TWIM is in SMBus mode. • SADR: Slave Address Address of the slave involved in the transfer. Bits 9-7 are don’t care if 7-bit addressing is used.
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UC3D 23.9.5 Name: Next Command Register NCMDR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 - 29 28 - 23 22 21 20 27 26 25 24 - - ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR.
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UC3D 23.9.6 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
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UC3D 23.9.7 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data to Transmit Write data to be transferred on the TWI bus here.
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UC3D 23.9.8 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - MENB 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY • MENB: Master Interface Enable 0: Master interface is disabled. 1: Master interface is enabled.
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UC3D • CCOMP: Command Complete This bit is one when the current command has completed successfully. This bit is zero if the command failed due to conditions such as a NAK receved from slave. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • CRDY: Ready for More Commands This bit is one when CMDR and/or NCMDR is ready to receive one or more commands. This bit is cleared when this is no longer true.
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UC3D 23.9.9 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
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UC3D 23.9.10 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
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UC3D 23.9.11 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 23.9.12 Name: Status Clear Register SCR Access Type : Write-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - - - CCOMP - - - Writing a zero to a bit in this register has no effect.
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UC3D 23.9.
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UC3D 23.9.14 Name: Version Register (VR) VR Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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UC3D 23.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 23-7. Module Clock Name Module Name Clock Name TWIM CLK_TWIM Table 23-8.
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UC3D 24. Two-wire Slave Interface (TWIS) Rev.: 1.2.0.1 24.1 Features • Compatible with I²C standard • • • • • • 24.
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UC3D 24.3 List of Abbreviations Table 24-3. 24.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 24-1. Block Diagram Peripheral Bus Bridge TWCK I/O Controller TWD Two-wire Interface Power Manager Interrupt Controller CLK_TWIS TWI Interrupt 24.
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UC3D Figure 24-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI serial EEPROM Slave 1 I²C RTC I²C LCD controller I²C temp. sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 24.6 I/O Lines Description Table 24-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 24.
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UC3D 24.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state. 24.7.4 DMA The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIS. 24.7.
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UC3D 24.8.2 Operation The TWIS has two modes of operation: • Slave transmitter mode • Slave receiver mode A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is assigned an address and responds to requests from the master. These modes are described in the following chapters. Figure 24-5. Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp.
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UC3D Figure 24-6. Bus Timing Diagram t HIGH t LOW S t HD:STA t LOW t SU:DAT t HD:DAT t t 24.8.2.2 t SU:DAT SU:STA SU:STO P Sr Setting Up and Performing a Transfer Operation of the TWIS is mainly controlled by the Control Register (CR). The following list presents the main steps in a typical communication: 3. Before any transfers can be performed, bus timings must be configured by writing to the Timing Register (TR).
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UC3D • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The Alert Response Address is checked for address match if CR.SMAL is one. • The Default Address is checked for address match if CR.SMDA is one. • The Host Header Address is checked for address match if CR.SMHH is one. 24.8.2.4 Clock Stretching Any slave or bus master taking part in a transfer may extend the TWCK low period at any time. The TWIS may extend the TWCK low period after each byte transfer if CR.
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UC3D ished, and the TWIS will wait for a STOP or REPEATED START. If an ACK bit is received, the SR.NAK bit remains LOW. The ACK indicates that more data should be transmitted, jump to step 2. At the end of the ACK/NAK clock cycle, the Byte Transfer Finished (SR.BTF) bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the TWIS to be LOW (see Figure 24-9). Also note that in the event that SR.NAK bit is set, it must not be cleared before the SR.
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UC3D Figure 24-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF TWD DATA (LSB) N P TWCK SR.NAK SR.BTF t1 t1 t1: (CLK_TWIS period) x 2 24.8.4 Slave Receiver Mode If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one CLK_TWIS cycle after the relevant address match bit in the same register is set). After the address phase, the following is repeated: 1.
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UC3D Figure 24-10. Slave Receiver with One Data Byte TWD S DADR W A DATA A P TCOMP RXRDY Read RHR Figure 24-11. Slave Receiver with Multiple Data Bytes TWD S DADR W A DATA n A DATA (n+1) A DAT A (n+m)-1 A DATA (n+m) P A TCOMP RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DAT A (n+m)-1 Read RHR DATA (n+m) 24.8.
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UC3D 3. Start the transfer by enabling the Peripheral DMA Controller to transmit. 4. Wait for the Peripheral DMA Controller end-of-transmit flag. 5. Disable the Peripheral DMA Controller. 24.8.6.2 Data Receive with the Peripheral DMA Controller 1. Initialize the receive Peripheral DMA Controller (memory pointers, size - 1, etc.). 2. Configure the TWIS (ADR, NBYTES, etc.). 3. Start the transfer by enabling the Peripheral DMA Controller to receive. 4.
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UC3D 24.8.8 Wakeup from Sleep Modes by TWI Address Match The TWIS is able to wake the device up from a sleep mode upon an address match, including sleep modes where CLK_TWIS is stopped. After detecting the START condition on the bus, The TWIS will stretch TWCK until CLK_TWIS has started. The time required for starting CLK_TWIS depends on which sleep mode the device is in. After CLK_TWIS has started, the TWIS releases its TWCK stretching and receives one byte of data on the bus.
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UC3D Table 24-5. Bus Events Event Effect Start, Repeated Start, or Stop received in illegal position on bus SR.BUSERR set. SR.STO and SR.TCOMP may or may not be set depending on the exact position of an illegal stop. Data is to be received in slave receiver mode, SR.STREN is set, and RHR is full TWCK is stretched until RHR has been read. Data is to be transmitted in slave receiver mode, SR.STREN is set, and THR is empty TWCK is stretched until THR has been written.
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UC3D 24.9 User Interface Table 24-6.
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UC3D 24.9.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - TENBIT 23 22 21 20 19 18 17 16 ADR[9:8] ADR[7:0] 15 14 13 12 11 10 9 8 SODR SOAM CUP ACK PECEN SMHH SMDA - 7 6 5 4 3 2 1 0 SWRST - - STREN GCMATCH SMATCH SMEN SEN • TENBIT: Ten Bit Address Match 0: Disables Ten Bit Address Match. 1: Enables Ten Bit Address Match.
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UC3D Writing a one to this bit resets the TWIS. • STREN: Clock Stretch Enable 0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. 1: Enables clock stretching if RHR/THR buffer full/empty. • GCMATCH: General Call Address Match 0: Causes the TWIS not to acknowledge the General Call Address. 1: Causes the TWIS to acknowledge the General Call Address. • SMATCH: Slave Address Match 0: Causes the TWIS not to acknowledge the Slave Address.
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UC3D 24.9.2 Name: NBYTES Register NBYTES Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 NBYTES • NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer.
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UC3D 24.9.3 Name: Timing Register TR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 SUDAT 15 14 13 12 TTOUT 7 6 5 4 TLOWS • EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter.
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UC3D 24.9.4 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
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UC3D 24.9.5 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here.
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UC3D 24.9.6 Name: Packet Error Check Register PECR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PEC • PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition.
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UC3D 24.9.7 Name: Status Register SR Access Type: Read-only Offset: 0x18 Reset Value: 0x000000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN TRA - TCOMP SEN TXRDY RXRDY • BTF: Byte Transfer Finished This bit is cleared when the corresponding bit in SCR is written to one.
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UC3D • SMBPECERR: SMBus PEC Error This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus PEC error has occurred. • SMBTOUT: SMBus Timeout This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus timeout has occurred. • NAK: NAK Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a NAK was received from the master during slave transmitter operation.
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UC3D 24.9.8 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
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UC3D 24.9.9 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
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UC3D 24.9.10 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 24.9.11 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - - - Writing a zero to a bit in this register has no effect.
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UC3D 24.9.
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UC3D 24.9.13 Name: Version Register (VR) VR Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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UC3D 24.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 24-7. Module Clock Name Module Name Clock Name TWIS CLK_TWIS Table 24-8.
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UC3D 25. Pulse Width Modulation Controller (PWMA) Rev: 2.0.0.0 25.1 Features • Left-aligned non-inverted 12-bit PWM • Common 12-bit timebase counter • • • • • 25.
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UC3D 25.3 Block Diagram Figure 25-1. PWMA Block Diagram PB IRQ PB Clock Domain Control CLK_PWMA TCLR TOP READY CHERR SPREAD WAVEXOR Interrupt Handling Channel Select Duty Cycle Adjust Channel_0 Sync Spread Spectrum Counter GCLK Timebase Counter PWM Blocks Duty Cycle Register TOFL ETV COMP Channel 0 Channel 1 Channel m GCLK Domain CWG PWMA[m:0] 25.4 I/O Lines Description Each channel outputs one PWM waveform on one external I/O line. Table 25-1. 25.
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UC3D 25.5.1 I/O Lines The pins used for interfacing the PWMA may be multiplexed with I/O Controller lines. The programmer must first program the I/O Controller to assign the desired PWMA pins to their peripheral function. It is only required to enable the PWMA outputs actually in use. 25.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the PWMA, the PWMA will stop functioning and resume operation after the system wakes up from sleep mode. 25.5.
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UC3D SPREAD field of CR (CR.SPREAD) is zero). When the timebase counter reaches its effective top value, it restarts counting from zero. The period of the PWMA output waveform is then: T PWMA = ( ETV + 1 ) ⋅ T GCLK The timebase counter can be reset by writing a one to the Timebase Clear bit in CR (CR.TCLR). Note that this can cause a glitch to the output PWM waveforms in use. 25.6.
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UC3D When writing a one to CR.TCLR, the timebase counter and the spread spectrum counter are reset at their lower limit values and the effective top value of the timebase counter will also be reset. 25.6.4 Duty Cycle and Waveform Properties Each PWM channel has its own duty cycle value (DCV) which is write-only and cannot be read out. The duty cycle value can be changed in two approaches as described in Section25.6.6. When the duty cycle value is zero, the PWM output is zero.
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UC3D (ISDUTY) register. Each channel has a corresponding enabling bit in the Interlinked Single Value Channel Set (ISCHSET) register(s). When a bit is written to one in the ISCHSET register, the duty cycle register for the corresponding channel will be updated with the value stored in the ISDUTY register. It can only be updated when the READY bit in the Status Register (SR.READY) is one, indicating that the PWMA is ready for writing. Figure 25-3 on page 509 shows the writing procedure.
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UC3D 25.6.7 Synchronization Both the timebase counter and the spread spectrum counter can be reset and the duty cycle registers can be written through the user interface of the module. This requires a synchronization between the PB and GCLK clock domains, which takes a few clock cycles of each clock domain. The BUSY bit in SR indicates when the synchronization is ongoing. Writing to the module while the BUSY bit is set will result in discarding the new value.
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UC3D 25.7 User Interface Table 25-3.
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UC3D 25.7.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - SPREAD[8] 23 22 21 20 19 18 17 16 11 10 9 8 SPREAD[7:0] 15 14 13 12 TOP 7 6 5 4 3 2 1 0 - - - - - - TCLR EN • SPREAD: Spread Spectrum Limit Value The spread spectrum limit value, together with the TOP field, defines the range for the spread spectrum counter.
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UC3D 25.7.2 Name: Interlinked Single Value Duty Register ISDUTY Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 DUTY[11:8] 3 2 DUTY[7:0] • DUTY: Duty Cycle Value The duty cycle value written to this field is written simultaneously to all channels selected in the ISCHSETm register.
PAGE 514
UC3D 25.7.3 Name: Interlinked Multiple Value Duty Register IMDUTY Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DUTY3 23 22 21 20 DUTY2 15 14 13 12 DUTY1 7 6 5 4 DUTY0 • DUTYn: Duty Cycle The value written to DUTY field n will be automatically written to the least significant 8 bits of the DUTYn register for a PWMA channel while the most significant 4bits of the DUTYn register are unchanged.
PAGE 515
UC3D 25.7.4 Name: Interlinked Multiple Value Channel Select IMCHSEL Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEL3 23 22 21 20 SEL2 15 14 13 12 SEL1 7 6 5 4 SEL0 • SELn: Channel Select The duty cycle of the PWMA channel SELn will be updated with the value stored in the DUTYn register when IMCHSEL is written. If SELn points to a non-implemented channel, the write will be discarded.
PAGE 516
UC3D 25.7.5 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - READY - TOFL Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 517
UC3D 25.7.6 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - READY - TOFL Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 518
UC3D 25.7.7 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - READY - TOFL 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one.
PAGE 519
UC3D 25.7.8 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - BUSY READY - TOFL • BUSY: Interface Busy This bit is automatically cleared when the interface is no longer busy.
PAGE 520
UC3D 25.7.9 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 1 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - READY - TOFL Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.
PAGE 521
UC3D 25.7.10 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x24 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CHANNELS • CHANNELS: Channels Implemented This field contains the number of channels implemented on the device.
PAGE 522
UC3D 25.7.11 Name: Version Register VERSION Access Type: Read-only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 523
UC3D 25.7.12 Name: Top Value Register TVR Access Type: Read/Write Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 TOP[11:8] 3 2 TOP[7:0] • TOP: Timebase Counter Top Value The top value for the timebase counter. The value written to the CR.
PAGE 524
UC3D 25.7.13 Name: Interlinked Single Value Channel Set ISCHSETm Access Type: Write-only Offset: 0x30+m*0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SET 23 22 21 20 SET 15 14 13 12 SET 7 6 5 4 SET • SET: Single Value Channel Set If the bit n in SET is one, the duty cycle of PWMA channel n will be updated with the value written to ISDUTY.
PAGE 525
UC3D 25.7.14 Name: Composite Waveform Generation CWG Access Type: Read/Write Offset: 0x3C+k*0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XOR 23 22 21 20 XOR 15 14 13 12 XOR 7 6 5 4 XOR • XOR: Pair Waveform XOR’ed If the bit n in XOR field is one, the pair of PWMA output waveforms will be XORed before output. The even number output will be the XOR’ed output and the odd number output will be reverse of it.
PAGE 526
UC3D 25.7.15 Name: Interlinked Multiple Value Duty0/1/2/3 Register DUTY0/1/2/3 Access Type: Write-only Offset: 0x80-0x8C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 DUTY[11:8] 3 2 DUTY[7:0] These registers allows up to 4 channels to be updated with a common 12-bits duty cycle value at a time.
PAGE 527
UC3D 25.8 Module Configuration The specific configuration for each PWMA instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 25-4. PWMA Configuration Feature PWMA Number of PWM channels 7 Table 25-5. PWMA Clocks Clock Name Description CLK_PWMA Clock for the PWMA bus interface GCLK_PWMA PWMA output clock source. The generic clock used for the PWMA is GCLK4 Table 25-6.
PAGE 528
UC3D 26. Timer/Counter (TC) Rev: 2.2.3.3 26.
PAGE 529
UC3D 26.3 Block Diagram Figure 26-1.
PAGE 530
UC3D 26.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. 26.5.3 Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TC before disabling the clock, to avoid freezing the TC in an undefined state. 26.5.
PAGE 531
UC3D 26.6.1.3 Clock selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for chaining by writing to the BMR register. See Figure 26-2 on page 531. Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5.
PAGE 532
UC3D • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode, it can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare bit in CMRn is written to one (CMRn.CPCDIS).
PAGE 533
UC3D 26.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • Software Trigger: each channel has a software trigger, available by writing a one to the Software Trigger Command bit in CCRn (CCRn.SWTRG). • SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger.
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UC3D 26.6.2.2 Trigger conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn (CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trigger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled.
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32133D–11/2011 TIOA TIOB SYNC MTIOA MTIOB TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 TIMER_CLOCK1 1 Edge Detector ETRGEDG SWTRG CLKI Edge Detector LDRA CLK Trig S R OVF If RA is Loaded CPCTRG 16-bit Counter RESET Q LDBSTOP R S CLKEN Edge Detector LDRB Capture Register A Q CLKSTA LDBDIS Capture Register B CLKDIS SR Timer/Counter Channel If RA is not Loaded or RB is Loaded ABETRG BURST TCCLKS Compare RC = Register C COVFS LDRBS INT UC3D Figure
PAGE 536
UC3D 26.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event.
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32133D–11/2011 TIOB SYNC XC2 XC1 TIMER_CLOCK5 XC0 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 EEVT Edge Detector EEVTEDG SWTRG ENETRG Trig CLK R S WAVSEL RESET 16-bit Counter WAVSEL Q OVF Compare RA = Q CLKSTA Register A SR Timer/Counter Channel 1 BURST CLKI Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC O utput Contr oller O utput Cont r oller TCCLKS TIOB M
PAGE 538
UC3D 26.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 26-6 on page 538. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 26-7 on page 539. RC Compare cannot be programmed to generate a trigger in this configuration.
PAGE 539
UC3D Figure 26-7. WAVSEL= 0 With Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA 26.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 26-8 on page 540.
PAGE 540
UC3D Figure 26-8. WAVSEL = 2 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 26-9. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA 26.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF.
PAGE 541
UC3D A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 26-11 on page 541. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 26-10.
PAGE 542
UC3D 26.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 26-12 on page 542. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 26-13 on page 543.
PAGE 543
UC3D Figure 26-13. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 26.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.EEVT) selects the external trigger.
PAGE 544
UC3D • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.
PAGE 545
UC3D 26.7 User Interface Table 26-3.
PAGE 546
UC3D Notes: 1. Read-only if CMRn.WAVE is zero. 2. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
PAGE 547
UC3D 26.7.1 Name: Channel Control Register CCR Access Type: Write-only Offset: 0x00 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - SWTRG CLKDIS CLKEN • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started.
PAGE 548
UC3D 26.7.
PAGE 549
UC3D 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 none 1 rising edge 2 falling edge 3 each edge • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs. • LDBSTOP: Counter Clock Stopped with RB Loading 1: Counter clock is stopped when RB loading occurs. 0: Counter clock is not stopped when RB loading occurs.
PAGE 550
UC3D 26.7.
PAGE 551
UC3D • BCPC: RC Compare Effect on TIOB BCPC Effect 0 none 1 set 2 clear 3 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 none 1 set 2 clear 3 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 none 1 set 2 clear 3 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 none 1 set 2 clear 3 toggle • ACPC: RC Compare Effect on TIOA ACPC Effect 0 none 1 set 2 clear 3 toggle 551 32133D–11/2011
PAGE 552
UC3D • ACPA: RA Compare Effect on TIOA ACPA Effect 0 none 1 set 2 clear 3 toggle • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled).
PAGE 553
UC3D • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection BURST Burst Signal Selection 0 The clock is not gated by an external signal. 1 XC0 is ANDed with the selected clock. 2 XC1 is ANDed with the selected clock. 3 XC2 is ANDed with the selected clock. • CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock.
PAGE 554
UC3D 26.7.4 Name: Channel Counter Value Register CV Access Type: Read-only Offset: 0x10 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 CV[15:8] 7 6 5 4 CV[7:0] • CV: Counter Value CV contains the counter value in real time.
PAGE 555
UC3D 26.7.5 Name: Channel Register A RA Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x14 + n * 0X40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RA[15:8] 7 6 5 4 RA[7:0] • RA: Register A RA contains the Register A value in real time.
PAGE 556
UC3D 26.7.6 Name: Channel Register B RB Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x18 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RB[15:8] 7 6 5 4 RB[7:0] • RB: Register B RB contains the Register B value in real time.
PAGE 557
UC3D 26.7.7 Name: Channel Register C RC Access Type: Read/Write Offset: 0x1C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RC[15:8] 7 6 5 4 RC[7:0] • RC: Register C RC contains the Register C value in real time.
PAGE 558
UC3D 26.7.8 Name: Channel Status Register SR Access Type: Read-only Offset: 0x20 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
PAGE 559
UC3D • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero.
PAGE 560
UC3D 26.7.9 Name: Channel Interrupt Enable Register IER Access Type: Write-only Offset: 0x24 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
PAGE 561
UC3D 26.7.10 Name: Channel Interrupt Disable Register IDR Access Type: Write-only Offset: 0x28 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
PAGE 562
UC3D 26.7.11 Name: Channel Interrupt Mask Register IMR Access Type: Read-only Offset: 0x2C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 563
UC3D 26.7.12 Name: Block Control Register BCR Access Type: Write-only Offset: 0xC0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - SYNC • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
PAGE 564
UC3D 26.7.
PAGE 565
UC3D • TC0XC0S: External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 0 TCLK0 1 none 2 TIOA1 3 TIOA2 565 32133D–11/2011
PAGE 566
UC3D 26.7.14 Name: Features Register FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - BRPBHSB UPDNIMPL 7 6 5 4 3 2 1 0 CTRSIZE • BRPBHSB: Bridge type is PB to HSB 1: Bridge type is PB to HSB. 0: Bridge type is not PB to HSB. • UPDNIMPL: Up/down is implemented 1: Up/down counter capability is implemented.
PAGE 567
UC3D 26.7.15 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
PAGE 568
UC3D 26.8 26.8.1 Module Configuration Clock Connections Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 26-4. Timer/Counter Clock Connections Module Source Name Connection TC Internal TIMER_CLOCK1 32 KHz oscillator clock (CLK_32K) TIMER_CLOCK2 PBA Clock / 2 TIMER_CLOCK3 PBA Clock / 8 TIMER_CLOCK4 PBA Clock / 32 TIMER_CLOCK5 PBA Clock / 128 External XC0 XC1 XC2 Table 26-5.
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UC3D 27. Capacitive Touch Module (CAT) Rev: 4.0.0.0 27.1 Features • • • • • 27.2 QTouch® method allows N touch sensors to be implemented using 2N physical pins One autonomous QTouch sensor operates without DMA or CPU intervention All QTouch sensors can operate in DMA-driven mode without CPU intervention External synchronization to reduce 50 or 60 Hz mains interference Spread spectrum sensor drive capability Overview The Capacitive Touch Module (CAT) senses touch on external capacitive touch sensors.
PAGE 570
UC3D 27.3 Block Diagram Figure 27-1. CAT Block Diagram Capacitive Touch Module (CAT) CLK_CAT Peripheral Bus Interface Registers Counters Finite State Machine Capacitor Charge and Discharge Sequence Generator CSAn I/O Controller Pins CSBn SYNC 27.4 I/O Lines Description Table 27-1. 27.
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UC3D Table 27-2.
PAGE 572
UC3D 27.5.2 Clocks The clock for the CAT module, CLK_CAT, is generated by the Power Manager (PM). This clock is turned on by default, and can be enabled and disabled in the PM. The user must ensure that CLK_CAT is enabled before using the CAT module. 27.5.3 Interrupts The CAT interrupt request line is connected to the interrupt controller. Using CAT interrupts requires the interrupt controller to be programmed first. 27.5.
PAGE 573
UC3D the Control Register (CTRL). After the module is enabled, the module will acquire data from the autonomous QTouch sensor and use it to determine whether the sensor is activated. The active/inactive status of the autonomous QTouch sensor is reported in the Status Register (SR), and it is also possible to configure the CAT to generate an interrupt whenever the status changes.
PAGE 574
UC3D The capacitive sensor charge length, discharge length, and settle length can be determined for each acquisition type using the CHLEN, DILEN, and SELEN fields in Configuration Registers 0 and 1. The lengths are specified in terms of prescaler clocks. 27.6.3 Capacitive Count Acquisition For the QTouch group A, and QTouch group B types of acquisition, the module acquires count values from the sensors, buffers them, and makes them available for reading in the ACOUNT register.
PAGE 575
UC3D Figure 27-3. CAT Acquisition and Processing Sequence Idle AISR written flag set? No Yes Autonomous touch enabled (ATEN)? No 27.6.5 Acquire counts Yes Acquire autonomous touch count Wait for all acquired counts to be transferred Update autonomous touch detection algorithm Clear AISR written flag Spread Spectrum Sensor Drive To reduce electromagnetic compatibility issues, the capacitive sensors can be driven with a spread spectrum signal.
PAGE 576
UC3D 9, 3, 4, 5, 6, 7, 8, 9, 3, 4, etc. MAXDEV must not exceed the value of (2(DIV+1)), or undefined behavior will occur. 27.6.6 Synchronization To prevent interference from the 50 or 60 Hz mains line the CAT can trigger acquisition on the SYNC signal. The SYNC signal should be derived from the mains line. The acquisition will trigger on a falling edge of this signal.
PAGE 577
UC3D 27.7 User Interface Table 27-3.
PAGE 578
UC3D 27.7.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 SWRST - - - - - - EN • SWRST: Software reset Writing a zero to this bit has no effect. Writing a one to this bit resets the module. The module will be disabled after the reset.
PAGE 579
UC3D 27.7.2 Name: Autonomous Touch Pin Selection Register ATPINS Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - ATEN 7 6 5 4 3 2 1 0 - - - ATSP • ATEN: Autonomous Touch Enable 0: Autonomous QTouch acquisition and detection is disabled.
PAGE 580
UC3D 27.7.3 Name: Pin Mode Registers 0, 1, and 2 PINMODE0, PINMODE1, and PINMODE2 Access Type: Read/Write Offset: 0x08, 0x0C, 0x74 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 23 22 21 20 - 15 14 13 SP[16] 12 11 10 9 8 3 2 1 0 SP[15:8] 7 6 5 4 SP[7:0] • SP: Sense Pair Mode Selection Each SP[n] bit determines the operation mode of sense pair n (CSAn and CSBn pins). The (PINMODE2.SP[n] PINMODE1.SP[n] PINMODE0.
PAGE 581
UC3D 27.7.4 Name: Autonomous/DMA Touch Configuration Register 0 ATCFG0 Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DIV[15:8] 23 22 21 20 DIV[7:0] 15 14 13 12 CHLEN 7 6 5 4 SELEN • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 1 MHz to produce the sampling clock.
PAGE 582
UC3D 27.7.5 Name: Autonomous/DMA Touch Configuration Register 1 ATCFG1 Access Type: Read/Write Offset: 0x14 Reset Value: 0x00000000 31 30 29 23 28 27 DISHIFT 22 21 26 - 20 25 24 SYNC SPREAD 19 18 17 16 11 10 9 8 3 2 1 0 DILEN 15 14 13 12 MAX[15:8] 7 6 5 4 MAX[7:0] • DISHIFT: Discharge Shift For the autonomous QTouch sensor and DMATouch sensors, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time.
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UC3D 27.7.6 Name: Autonomous/DMA Touch Configuration Register 2 ATCFG2 Access Type: Read/Write Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 23 22 21 20 15 14 FILTER 13 12 11 10 9 8 3 2 1 0 OUTSENS 7 6 5 4 SENSE • FILTER: Autonomous Touch Filter Setting For the autonomous QTouch sensor and DMATouch sensors, specifies how many positive detects in a row the CAT needs to have on the sensor before reporting it as a touch.
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UC3D 27.7.7 Name: Autonomous/DMA Touch Configuration Register 3 ATCFG3 Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 23 22 21 20 PTHR 15 14 13 12 PDRIFT 7 6 5 4 NDRIFT • PTHR: Positive Recalibration Threshold For the autonomous QTouch sensor and DMATouch sensors, specifies how far a sensor’s signal must move in a positive direction from the reference in order to cause a recalibration.
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UC3D 27.7.8 Name: Touch Group x Configuration Register 0 TGxCFG0 Access Type: Read/Write Offset: 0x20, 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DIV[15:8] 23 22 21 20 DIV[7:0] 15 14 13 12 CHLEN 7 6 5 4 SELEN • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 1 MHz to produce the sampling clock.
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UC3D 27.7.9 Name: Touch Group x Configuration Register 1 TGxCFG1 Access Type: Read/Write Offset: 0x24, 0x2C Reset Value: 0x00000000 31 30 - - 23 22 29 28 DISHIFT 21 20 27 26 25 24 - - SYNC SPREAD 19 18 17 16 11 10 9 8 3 2 1 0 DILEN 15 14 13 12 MAX[15:8] 7 6 5 4 MAX[7:0] • DISHIFT: Discharge Shift For the sensors in QTouch group x, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time.
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UC3D 27.7.10 Name: Status Register SR Access Type: Read-only Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - DMATSR DMATSW 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - MBLREQ ATSTATE ATSC ATCAL ENABLED • DMATSC: DMATouch Sensor State Change 0: No change in the DMATSS register. 1: One or more bits have changed in the DMATSS register.
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UC3D • ATCAL: Autonomous Touch Calibration Ongoing 0: The autonomous QTouch sensor is not calibrating. 1: The autonomous QTouch sensor is calibrating. • ENABLED: Module Enabled 0: The module is disabled. 1: The module is enabled.
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UC3D 27.7.11 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x40 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - - - ATSC ATCAL - Writing a zero to a bit in this register has no effect.
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UC3D 27.7.12 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x44 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - - - ATSC ATCAL - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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UC3D 27.7.13 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x48 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - - - ATSC ATCAL - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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UC3D 27.7.14 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - - - ATSC ATCAL - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 27.7.15 Name: Acquisition Initiation and Selection Register AISR Access Type: Read/Write Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 23 22 21 20 - 15 14 13 12 - 7 6 5 4 - ACQSEL • ACQSEL: Acquisition Type Selection A write to this register initiates an acquisition of the following type: 00: QTouch Group A. 01: QTouch Group B. 10: Undefined behavior. 11: Undefined behavior.
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UC3D 27.7.16 Name: Acquired Count Register ACOUNT Access Type: Read-only Offset: 0x54 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 SPORX 15 14 13 12 COUNT[15:8] 7 6 5 4 COUNT[7:0] • SPORX: Sensor pair index The sensor pair index (for QTouch method) associated with this count value. • COUNT: Count value The signal (number of counts) acquired on the channel specified in the SPORX and Y fields.
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UC3D 27.7.17 Name: Spread Spectrum Configuration Register SSCFG Access Type: Read/Write Offset: 0x60 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 MAXDEV • MAXDEV: Maximum Deviation When spread spectrum burst is enabled, MAXDEV indicates the maximum number of prescaled clock cycles the burst pulse will be extended or shortened.
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UC3D 27.7.18 Name: CSA Resistor Control Register CSARES Access Type: Read/Write Offset: 0x64 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 23 22 21 20 - 15 14 13 RES[16] 12 11 10 9 8 3 2 1 0 RES[15:8] 7 6 5 4 RES[7:0] • RES: Resistive Drive Enable When RES[n] is 0, CSA[n] has the same drive properties as normal I/O pads. When RES[n] is 1, CSA[n] has a nominal output resistance of 1kOhm during the burst phase.
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UC3D 27.7.19 Name: CSB Resistor Control Register CSBRES Access Type: Read/Write Offset: 0x68 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 23 22 21 20 - 15 14 13 RES[16] 12 11 10 9 8 3 2 1 0 RES[15:8] 7 6 5 4 RES[7:0] • RES: Resistive Drive Enable When RES[n] is 0, CSB[n] has the same drive properties as normal I/O pads. When RES[n] is 1, CSB[n] has a nominal output resistance of 1kOhm during the burst phase.
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UC3D 27.7.20 Name: Autonomous Touch Base Count Register ATBASE Access Type: Read-only Offset: 0x6C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 23 22 21 20 - 15 14 13 12 COUNT[15:8] 7 6 5 4 COUNT[7:0] • COUNT: Count value The base count currently stored by the autonomous touch sensor. This is useful for autonomous touch debugging purposes.
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UC3D 27.7.21 Name: Autonomous Touch Current Count Register ATCURR Access Type: Read-only Offset: 0x70 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 23 22 21 20 - 15 14 13 12 COUNT[15:8] 7 6 5 4 COUNT[7:0] • COUNT: Count value The current count acquired by the autonomous touch sensor. This is useful for autonomous touch debugging purposes.
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UC3D 27.7.22 Name: DMATouch State Write Register DMATSW Access Type: Write-only Offset: 0x78 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - NOTINCAL 23 22 21 20 19 18 17 16 10 9 8 2 1 0 DETCNT[23:16] 15 14 13 12 11 BASECNT[15:8] 7 6 5 4 3 BASECNT[7:0] • NOTINCAL: Not in Calibration Mode 0: Calibration should be performed on the next iteration of the DMATouch algorithm.
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UC3D 27.7.23 Name: DMA Touch State Read Register DMATSR Access Type: Read/Write Offset: 0x7C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - NOTINCAL 23 22 21 20 19 18 17 16 10 9 8 2 1 0 DETCNT[23:16] 15 14 13 12 11 BASECNT[15:8] 7 6 5 4 3 BASECNT[7:0] • NOTINCAL: Not in Calibration Mode 0: Calibration should be performed on the next iteration of the DMATouch algorithm.
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UC3D 27.7.24 Name: DMATouch Sensor Status Register DMATSS Access Type: Read-only Offset: 0xA0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SS[31:24] 23 22 21 20 SS[23:16] 15 14 13 12 SS[15:8] 7 6 5 4 SS[7:0] • SS: Sensor Status 0: The DMATouch sensor is not active, i.e. the button is currently not pushed. 1: The DMATouch sensor is active, i.e. the button is currently pushed.
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UC3D 27.7.25 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0xF8 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SP[31:24] 23 22 21 20 SP[23:16] 15 14 13 12 SP[15:8] 7 6 5 4 SP[7:0] • SP[n]: Sensor pair implemented 0: The corresponding sensor pair is not implemented 1: The corresponding sensor pair is implemented.
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UC3D 27.7.26 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 27.8 Module Configuration The specific configuration of the CAT module is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 27-4. Module Configuration Feature CAT Number of touch sensors Allows up to 25 buttons for 64 pins packages. Allows up to 17 buttons for 48 pins packages. Table 27-5. Module clock name Module name Clock name CAT CLK_CAT Table 27-6.
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UC3D 28. ADC Interface (ADCIFD) Rev. 1.0.0.0 28.1 Feature • Multi-channel single-ended Analog-to-Digital Converter with up to 10-bit resolution • Sequencer handling multiple conversions • Numerous trigger sources • • • • 28.
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UC3D 28.3 Block diagram Figure 28-1. ADCIFD block diagram ADCIFD Internal Trigger Trigger Selection ADTRG Timer Sequencer VDDANA GCLK ADVREF DMA request AD0 Interrupt Request AD3 Analog multiplexer AD2 GPIO Controller AD1 Successive Approximation Register Analog-to-Digital Converter User Interface Adcifd_pevc_eoc Adcifd_pevc_wm CLK_ADCIFD ADn 28.4 I/O Lines Description Table 28-1.
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UC3D 28.5 28.5.1 Product dependencies I/O Lines The pins used for interfacing the ADCIFD may be multiplexed with I/O Controller lines. The programmer must first program the I/O controller to assign the desired ADCIFD pins to their peripheral function. If I/O lines of the ADCIFD are not used by the application, they can be used for other purposes by the I/O controller. Not all ADCIFD outputs may be enabled.
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UC3D to be set. If the power reduction mode is on, only SR.EN can tell if the ADCIFD is ready for operation since startup-time will be performed only when a sequencer trigger event occurs. Please note that all ADCIFD controls will be ignored until SR.EN goes to ‘1’. Before the ADCIFD can be used, the I/O Controller must be configured correctly and the Reference Voltage (ADVREF) signal must be connected. Refer to I/O Controller section for details.
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UC3D 28.6.4 ADC Sequencer operating modes 28.6.4.1 General The ADC sequencer consists in a mult-conversion sequencer. A sequence consists in a set of conversions to perform successively. The maximum number of conversions is 16, the actual number of conversions is given by the CNVNB field in the SEQCFG register (SEQCFG.CNVNB). After a conversion, the digital value of the selected channel is stored in the Last Converted Value register (LCV).
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UC3D logic waits during this time and then starts the conversion of the enabled channels. When conversions of all enabled channels are complete, the ADC is deactivated until the next trigger event. Before entering power reduction mode the user must make sure the ADCIFD is idle and that the Analog-to-Digital Converter cell is inactive. To deactivate the Analog-to-Digital Converter cell the PRM bit in the ADC Configuration Register (CFG) must be written to one and the ADCIFD must be idle.
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UC3D 28.6.12 Conversion results If the Half Word Left Adjust (HWLA) bit in the SEQCFG register is set, then the result will be left adjusted on the 16 lower bits of the LCV register. Otherwise, results will be right-adjusted.All SRES + HWLA ( 16 – SRES ) V ( AD ) Code = --------------------------------- × 2 V ( ADVREF ) conversion results are signed in two's complement representation. Extra bits depending on resolution and left adjust settings are padded with zeroes. 28.6.
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UC3D 28.6.16 Window monitor The window monitor monitors ADC results and make the ADCIFD behave as an analog comparator. Configuration is done by writing appropriately the Window Configuration Register (WCFG) and the Window Thresholds Register (WTH). When writing a one in the Monitor Filter Mode bit in the WCFG register (WCFG.MFM) , conversions are filtered using its index in the sequence. Otherwise, no filtering is applied, monitoring is performed on every conversion.
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UC3D Table 28-3. Line ADCIFD interrupt group Line Description Related Status Sequencer start of sequence (SSOS) Sequencer end of sequence (SEOS) 0 Sequencer Sequencer end of conversion (SEOC) Sequencer (last converted value) overrun (LOVR) Sequencer missed trigger event (SMTRG) 28.6.18 1 Timing 2 Window Start-up done Timer time-out Window monitor Conversion Performances For performance and electrical characteristics of the ADCIFD, refer to the Electrical Characteristics chapter.
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UC3D 28.7 User Interface Table 28-4.
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UC3D 28.7.1 Name : Control Register CR Access Type : Write-Only Offset : 0x00 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - DIS EN 7 6 5 4 3 2 1 0 - - - - TSTART TSTOP STRIG SWRST Writing a zero to any of those bits in this register has no effect.
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UC3D 28.7.
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UC3D 28.7.
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UC3D This bit is cleared when the corresponding bit in SCR is written to one • LOVR:Sequencer last converted value overrun This bit is set when an overrun error occurs on the LCV register This bit is cleared when the corresponding bit in SCR is written to one • SEOC:Sequencer end of conversion This bit is set when an end of conversion occurs This bit is cleared when the corresponding bit in SCR is written to one • SEOS:Sequencer end of sequence This bit is set when an end of sequence occurs This bit is cle
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UC3D 28.7.4 Name : Status Clear Register SCR Access Type : Write-Only Offset : 0x0C Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TTO SUTD SMTRG WM LOVR SEOC SEOS SSOS Writing a zero to a bit in this register has no effect.
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UC3D 28.7.5 Name : Status Set Register SSR Access Type : Write-Only Offset : 0x10 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TTO SUTD SMTRG WM LOVR SEOC SEOS SSOS Writing a zero to a bit in this register has no effect.
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UC3D 28.7.
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UC3D • HWLA:Half Word Left Adjust 1 : enables the HWLA mode 0 : disables the HWLA mode • SA:Software Acknowledge 1 : enables the SA mode 0 : disables the SA mode 623 32133D–11/2011
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UC3D 28.7.
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UC3D 28.7.
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UC3D 28.7.
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UC3D 28.7.
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UC3D 28.7.
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UC3D 28.7.
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UC3D 28.7.13 Name : Sequencer last converted value LCV Access Type : Read-Only Offset : 0x30 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LCV 7 6 5 4 LCV • LCV:Last converted value This field is set by hardware to the last sequencer converted value depending on precision and on the choosen left adjustment mode (SEQCFG.HWLA).
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UC3D 28.7.14 Name : Interrupt enable register IER Access Type : Write-Only Offset : 0x34 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - 7 6 5 4 3 2 1 0 TTO SUTD SMTRG WM LOVR SEOC SEOS SSOS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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UC3D 28.7.15 Name : Interrupt disable register IDR Access Type : Write-Only Offset : 0x38 Reset Value : 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - 7 6 5 4 3 2 1 0 TTO SUTD SMTRG WM LOVR SEOC SEOS SSOS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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UC3D 28.7.16 Name : Interrupt mask register IMR Access Type : Read-Only Offset : 0x3C Reset Value : 0x00000000 31 30 29 28 - - - 23 22 21 20 - - - - 15 14 13 12 - - - 7 6 5 4 TTO SUTD SMTRG WM 27 26 25 24 - - - 18 17 16 - - - 10 9 8 - - - 3 2 1 0 LOVR SEOC SEOS SSOS 19 11 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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UC3D 28.7.17 Name : Module Version VERSION Access Type : Read-Only Offset : 0x40 Reset Value : - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION 3 2 VERSION • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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UC3D 28.7.
PAGE 636
UC3D 28.8Module configuration The specific configuration for each ADC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 28-5. Module configuration Feature Connected to Internal Trigger TC0, output A0 Table 28-6. ADCIFD Clocks Clock Name Description CLK_ADCIFD Clock for the ADCIFD bus interface GCLK_ADCIFD Conversion clock.
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UC3D 29. Glue Logic Controller (GLOC) Rev: 1.0.1.0 29.1 Features • • • • 29.2 Glue logic for general purpose PCB design Programmable lookup table Up to four inputs supported per lookup table Optional filtering of output Overview The Glue Logic Controller (GLOC) contains programmable logic which can be connected to the device pins. This allows the user to eliminate logic gates for simple glue logic functions on the PCB. The GLOC consists of a number of lookup table (LUT) units.
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UC3D 29.4 I/O Lines Description Table 29-1. I/O Lines Description Pin Name Pin Description Type IN0-INm Inputs to lookup tables Input OUT0-OUTn Output from lookup tables Output Each LUT have 4 inputs and one output. The inputs and outputs for the LUTs are mapped sequentially to the inputs and outputs. This means that LUT0 is connected to IN0 to IN3 and OUT0. LUT1 is connected to IN4 to IN7 and OUT1. In general, LUTn is connected to IN[4n] to IN[4n+3] and OUTn. 29.
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UC3D 29.6.2 Configuring the Lookup Table The lookup table in each LUT unit can generate any logic expression OUT as a function of up to four inputs, IN[3:0]. The truth table for the expression is written to the TRUTH register for the LUT. Table 29-2 shows the truth table for LUT0. The truth table for LUTn is written to TRUTHn, and the corresponding input and outputs will be IN[4n] to IN[4n+3] and OUTn. Table 29-2. 29.6.
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UC3D 29.7 User Interface Table 29-3. GLOC Register Memory Map Offset Register Register Name Access Reset 0x00+n*0x08 Control Register n CRn Read/Write 0x00000000 0x04+n*0x08 Truth Table Register n TRUTHn Read/Write 0x00000000 0x38 Parameter Register PARAMETER Read-only - (1) 0x3C Version Register VERSION Read-only - (1) Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
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UC3D 29.7.1 Name: Control Register n CRn Access Type: Read/Write Offset: 0x00+n*0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 FILTEN - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - AEN • FILTEN: Filter Enable 1: The output is glitch filtered 0: The output is not glitch filtered • AEN: Enable IN Inputs Input IN[n] is enabled when AEN[n] is one.
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UC3D 29.7.
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UC3D 29.7.3 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x38 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 LUTS • LUTS: Lookup Table Units Implemented This field contains the number of lookup table units implemented in this device.
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UC3D 29.7.4 Name: VERSION Register VERSION Access Type: Read-only Offset: 0x3C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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UC3D 29.8 Module Configuration The specific configuration for each GLOC instance is listed in the following tables.The GLOC bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 29-4. GLOC Configuration Feature GLOC Number of LUT units 4 Table 29-5. GLOC Clock Name Clock Name Description CLK_GLOC Clock for the GLOC bus interface GCLK_GLOC Generic clock used for the output filter feature.
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UC3D 30. aWire UART (AW) Rev: 2.3.0.0 30.1 Features • Asynchronous receiver or transmitter when the aWire system is not used for debugging. • One- or two-pin operation supported. 30.2 Overview If the AW is not used for debugging, the aWire UART can be used by the user to send or receive data with one start bit, eight data bits, no parity bits, and one stop bit. This can be controlled through the aWire UART user interface. This chapter only describes the aWire UART user interface.
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UC3D 30.4 I/O Lines Description Table 30-1. I/O Lines Description Name Description Type DATA aWire data multiplexed with the RESET_N pin. Input/Output 30.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 30.5.1 I/O Lines The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default function of this pin.
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UC3D 30.6.1 How to Initialize The Module To initialize the aWire UART user interface the user must first enable the clock by writing a one to the Clock Enable bit in the Clock Request Register (CLKR.CLKEN) and wait for the Clock Enable bit in the Status Register (SR.CENABLED) to be set. After doing this either receive, transmit or receive with resync must be selected by writing the corresponding value into the Mode field of the Control (CTRL.MODE) Register.
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UC3D 30.6.6 Interrupts To make the CPU able to do other things while waiting for the aWire UART user interface to finish its operations the aWire UART user interface supports generating interrupts. All status bits in the Status Register can be used as interrupt sources, except the SR.BUSY and SR.CENABLED bits. To enable an interrupt the user must write a one to the corresponding bit in the Interrupt Enable Register (IER).
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UC3D 30.7 User Interface Table 30-2.
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UC3D 30.7.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - MODE • MODE: aWire UART user interface mode Table 30-3. aWire UART user interface Modes MODE Mode Description 0 Disabled 1 Receive 2 Transmit 3 Receive with resync.
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UC3D 30.7.2 Name: Status Register SR Access Type: Read-only Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - CENABLED - BUSY • TRMIS: Transmit Mismatch 0: No transfers mismatches. 1: The transceiver was active when receiving.
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UC3D This bit is set when the clock is disabled. This bit is cleared when the clock is enabled. • BUSY: Synchronizer Busy 0: The asynchronous interface is ready to accept more data. 1: The asynchronous interface is busy and will block writes to CTRL, BRR, and THR. This bit is set when the asynchronous interface becomes busy. This bit is cleared when the asynchronous interface becomes ready.
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UC3D 30.7.3 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect.
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UC3D 30.7.4 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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UC3D 30.7.5 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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UC3D 30.7.6 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 658
UC3D 30.7.7 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data The last byte received.
PAGE 659
UC3D 30.7.8 Name: Transmit Holding Register THR Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Transmit Data The data to send.
PAGE 660
UC3D 30.7.9 Name: Baud Rate Register BRR Access Type: Read/Write Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 BR[15:8] 7 6 5 4 BR[7:0] • BR: Baud Rate The baud rate ( f br ) of the transmission, calculated using the following formula ( f aw is the RC120M frequency): 8f aw f br = ----------BR BR should not be set to a value smaller than 32.
PAGE 661
UC3D 30.7.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x24 Reset Value: 0x00000200 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 662
UC3D 30.7.11 Name: Clock Request Register CLKR Access Type: Read/Write Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CLKEN • CLKEN: Clock Enable 0: The aWire clock is disabled. 1: The aWire clock is enabled. Writing a zero to this bit will disable the aWire clock.
PAGE 663
UC3D 30.8 Module Configuration The specific configuration for each aWire instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 30-4. Module clock name Module name Clock name aWire CLK_AW Table 30-5.
PAGE 664
UC3D 31. Programming and Debugging 31.1 Overview The UC3D supports programming and debugging through two interfaces, JTAG or aWire ™. JTAG is an industry standard interface and allows boundary scan for PCB testing, as well as daisy-chaining of multiple devices on the PCB. aWire is an Atmel proprietary protocol which offers higher throughput and robust communication, and does not require application pins to be reserved.
PAGE 665
UC3D Table 31-1. 31.2.2 SAB Slaves, Addresses and Descriptions Slave Address [35:32] Description HSB 0x5 Alternative mapping for HSB space, for compatibility with other AVR32 devices. Memory Service Unit 0x6 Memory Service Unit registers Reserved Other Unused SAB Security Restrictions The Service Access bus can be restricted by internal security measures. A short description of the security measures are found in the table below. 31.2.2.
PAGE 666
UC3D Table 31-4.
PAGE 667
UC3D 31.3 On-Chip Debug Rev: 2.1.2.0 31.3.1 Features • • • • • • • • 31.3.2 Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.
PAGE 668
UC3D selectable by OCD Registers, minimizing the chance that the AUX port will need to be shared with an application. Table 31-5. 31.3.
PAGE 669
UC3D 31.3.5 Block Diagram Figure 31-1. On-Chip Debug Block Diagram aWire JTAG aWire JTAG AUX On-Chip Debug Memory Service Unit Service Access Bus Transmit Queue Watchpoints Debug PC Debug Instruction Breakpoints CPU 31.3.6 Program Trace Internal SRAM HSB Bus Matrix Data Trace Ownership Trace Memories and peripherals SAB-based Debug Features A debugger can control all OCD features by writing OCD registers over the SAB interface.
PAGE 670
UC3D Figure 31-2. JTAG-based Debugger PC JTAG -based debug tool 10-pin IDC JTAG 32-bit AVR Figure 31-3. aWire-based Debugger PC aWire-based debug tool aWire 32-bit AVR 31.3.6.1 Debug Communication Channel The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and debugger. The registers can be used to exchange data between the CPU and the debugmaster, both runtime as well as in debug mode.
PAGE 671
UC3D The OCD system can generate an interrupt to the CPU when DCCPU is read and when DCEMU is written. This enables the user to build a custum debug protocol using only these registers. The DCCPU and DCEMU registers are available even when the security bit in the flash is active. For more information refer to the AVR32UC Technical Reference Manual. 31.3.6.2 Breakpoints One of the most fundamental debug features is the ability to halt the CPU, to examine registers and the state of the system.
PAGE 672
UC3D 31.3.7.1 Cyclic Redundancy Check (CRC) The MSU can be used to automatically calculate the CRC of a block of data in memory. The MSU will then read out each word in the specified memory block and report the CRC32-value in an MSU register. 31.3.7.2 NanoTrace The MSU additionally supports NanoTrace. This is a 32-bit AVR-specific feature, in which trace data is output to memory instead of the AUX port.
PAGE 673
UC3D Figure 31-4. AUX+JTAG Based Debugger PC T ra c e b u ffe r A U X +JTA G d e b u g to o l M ic t o r 3 8 AUX h ig h s p e e d JTA G AVR 32 31.3.8.1 Trace Operation Trace features are enabled by writing OCD registers by the debugger. The OCD extracts the trace information from the CPU, compresses this information and formats it into variable-length messages according to the Nexus standard. The messages are buffered in a 16-frame transmit queue, and are output on the AUX port one frame at a time.
PAGE 674
UC3D are controlled by a pair of OCD registers which determine the range of addresses (or single address) which should produce data trace messages. 31.3.8.4 Ownership Trace Program and data trace operate on virtual addresses. In cases where an operating system runs several processes in overlapping virtual memory segments, the Ownership Trace feature can be used to identify the process switch.
PAGE 675
UC3D 31.4 aWire Debug Interface (AW) Rev.: 2.3.0.1 31.4.1 Features • • • • • • • • 31.4.2 Single pin debug system. Half Duplex asynchronous communication (UART compatible). Full duplex mode for direct UART connection. Compatible with JTAG functionality, except boundary scan. Failsafe packet-oriented protocol. Read and write on-chip memory and program on-chip flash and fuses through SAB interface. On-Chip Debug access through SAB interface.
PAGE 676
UC3D 31.4.3 Block Diagram Figure 31-5. aWire Debug Interface Block Diagram PB aWire Debug Interface Flash Controller CHIP_ERASE command AW User Interface CPU HALT command RESET command Power Manager External reset AW_ENABLE AW CONTROL Reset filter RESET_N Baudrate Detector SAB interface UART RW SZ ADDR DATA CRC SAB 31.4.4 I/O Lines Description Table 31-6. I/O Lines Description Name Description Type DATA aWire data multiplexed with the RESET_N pin.
PAGE 677
UC3D 31.4.5.1 I/O Lines The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default function of this pin. To enable the aWire functionality on the RESET_N pin the user must enable the AW either by sending the enable sequence over the RESET_N pin from an external aWire master or by enabling the aWire user interface. In 2-pin mode data is received on the RESET_N line, but transmitted on the DATAOUT line.
PAGE 678
UC3D The CRC is calculated from the command/response, length, and data fields. The polynomial used is the FCS16 (or CRC-16-CCIT) in reverse mode (0x8408) and the starting value is 0x0000. Example command Below is an example command from the master with additional data. Figure 31-6. Example Command baud_rate_clk data_pin field ... sync(0x55) command(0x81) length(MSB) length(lsb) data(MSB) data(LSB) CRC(MSB) CRC(lsb) ...
PAGE 679
UC3D RESET_N pin should not be connected to an external reset circuitry, but disconnected via a switch or a jumper to avoid drive contention and speed problems. Figure 31-8. Reset Circuitry and aWire. MCU aWire master connector Board Reset Circuitry Jumper AW Debug Interface RESET_N Power Manager 31.4.6.3 Initializing the AW To enable AW, the user has to send a 0x55 pattern with a baudrate of 1 kHz on the RESET_N pin.
PAGE 680
UC3D TUNE × f br f aw = ----------------------------8 Where f br is the baud rate frequency and f aw is the frequency of the internal RC120M. TUNE is the value returned by the BAUD_RATE response. To find the max frequency the user can issue the TUNE command to the AW to make it return the TUNE value. This value can be used to compute the f aw . The maximum operational frequency ( f brmax ) is then: f aw f brmax = ------4 31.4.6.
PAGE 681
UC3D The aWire master should adjust its baudrate or delay between bytes when doing SAB accesses to ensure that the SAB is not overwhelmed with data. Error Reporting If a write is performed on a non-existing memory location the SAB interface will respond with an error. If this happens, all further writes in this command will not be performed and the error and number of bytes written is reported in the MEMORY_READWRITE_STATUS message from the AW after the write.
PAGE 682
UC3D Table 31-8. aWire Command Summary COMMAND Instruction Description 0x82 HALT Issues a halt command to the device. 0x83 RESET Issues a reset to the Reset Controller. 0x84 SET_GUARD_TIME Sets the guard time for the AW. All aWire commands are described below, with a summary in table form. Table 31-9. Command/Response Description Notation Command/Response Description Command/Response value Shows the command/response value to put into the command/response field of the packet.
PAGE 683
UC3D 31.4.7.4 TUNE Asks the AW for the current baud rate counter value. Table 31-13. TUNE Details 31.4.7.5 Command Details Command value 0x04 Additional data N/A Possible responses 0xC3: BAUD_RATE (Section 31.4.8.6) 0x41: NACK (Section 31.4.8.2) MEMORY_SPEED_REQUEST Asks the AW for the relative speed between the aWire clock (RC120M) and the SAB interface. Table 31-14. MEMORY_SPEED_REQUEST Details 31.4.7.
PAGE 684
UC3D 31.4.7.8 2_PIN_MODE Enables the DATAOUT pin as an output pin. All responses sent from the aWire slave will be sent on this pin, instead of the RESET_N pin, starting with the ACK for the 2_PIN_MODE command. Table 31-17. DISABLE Details 31.4.7.9 Command Details Command value 0x07 Additional data N/A Possible responses 0x40: ACK (Section 31.4.8.1) 0x41: NACK (Section 31.4.8.2) MEMORY_WRITE This command enables programming of memory/writing to registers on the SAB.
PAGE 685
UC3D 14. 0xXX (CRC MSB) 15. 0xXX (CRC LSB) The length field is set to 0x0009 because there are 9 bytes of additional data: 5 address and size bytes and 4 bytes of data. The address and size field indicates that words should be written to address 0x500000004. The data written to 0x500000004 is 0xCAFEBABE. Table 31-19. MEMORY_WRITE Details 31.4.7.10 Command Details Command value 0x80 Additional data Size, Address and Data Possible responses 0xC2: MEMORY_READWRITE_STATUS (Section 31.4.8.
PAGE 686
UC3D 11. 0x04 12. 0xXX (CRC MSB) 13. 0xXX (CRC LSB) The length field is set to 0x0007 because there are 7 bytes of additional data: 5 bytes of address and size and 2 bytes with the number of bytes to read. The address and size field indicates one word (four bytes) should be read from address 0x500000004. Table 31-21. MEMORY_READ Details 31.4.7.11 Command Details Command value 0x81 Additional data Size, Address and Length Possible responses 0xC1: MEMDATA (Section 31.4.8.
PAGE 687
UC3D 31.4.7.13 SET_GUARD_TIME Sets the guard time value in the AW, i.e. how long the AW will wait before starting its transfer after the master has finished. The guard time can be either 0x00 (128 bit lengths), 0x01 (16 bit lengths), 0x2 (4 bit lengths) or 0x3 (1 bit length). Table 31-24. SET_GUARD_TIME Details 31.4.8 Command Details Command value 0x84 Additional data Guard time Possible responses 0x40: ACK (Section 31.4.8.1) 0x41: NACK (Section 31.4.8.
PAGE 688
UC3D 31.4.8.3 IDCODE The JTAG idcode for this device. Table 31-28. IDCODE Details 31.4.8.4 Response Details Response value 0xC0 Additional data JTAG idcode MEMDATA The data read from the address specified by the MEMORY_READ command. The last 3 bytes are status bytes from the read. The first status byte is the status of the command described in the table below. The last 2 bytes are the number of remaining data bytes to be sent in the data field of the packet when the error occurred.
PAGE 689
UC3D The error occurred after reading 2 bytes on the SAB. The rest of the bytes read are undefined. The status byte indicates the error and the bytes remaining indicates how many bytes were remaining to be sent of the data field of the packet when the error occurred. Table 31-29. MEMDATA Status Byte status byte Description 0x00 Read successful 0x01 SAB busy 0x02 Bus error (wrong address) Other Reserved Table 31-30. MEMDATA Details 31.4.8.
PAGE 690
UC3D 31.4.8.7 STATUS_INFO A status message from AW. Table 31-34. STATUS_INFO Contents Bit number Name Description 15-9 Reserved 8 Protected The protection bit in the internal flash is set. SAB access is restricted. This bit will read as one during reset. 7 SAB busy The SAB bus is busy with a previous transfer. This could indicate that the CPU is running on a very slow clock, the CPU clock has stopped for some reason or that the part is in constant reset.
PAGE 691
UC3D 31.5 JTAG and Boundary-scan (JTAG) Rev: 2.2.2.4 31.5.1 Features • IEEE1149.1 compliant JTAG Interface • Boundary-scan Chain for board-level testing • Direct memory access and programming capabilities through JTAG Interface 31.5.2 Overview The JTAG Interface offers a four pin programming and debug solution, including boundary-scan support for board-level testing. Figure 31-9 on page 692 shows how the JTAG is connected in an 32-bit AVR device.
PAGE 692
UC3D 31.5.3 Block Diagram Figure 31-9. JTAG and Boundary-scan Access 32-bit AVR device JTAG JTAG master Boundary scan enable TAP Controller TDO TDI JTAG Pins TMS TCK TCK TMS TDI TDO Instruction register scan enable Data register scan enable Instruction Register TMS TCK TDO TDI JTAG data registers 2nd JTAG device Device Identification Register Boundary Scan Chain Pins and analog blocks By-pass Register Reset Register Part specific registers ... Service Access Bus interface SAB 31.5.
PAGE 693
UC3D 31.5.5.1 I/O Lines The TMS, TDI, TDO, and TCK pins are multiplexed with I/O lines. When the JTAG is used the associated pins must be enabled. To enable the JTAG pins, refer to Section 31.5.7. While using the multiplexed JTAG lines all normal peripheral activity on these lines is disabled. The user must make sure that no external peripheral is blocking the JTAG lines while debugging. 31.5.5.
PAGE 694
UC3D Figure 31-10.
PAGE 695
UC3D 31.5.7 How to Initialize the Module To enable the JTAG pins the TCK pin must be held low while the RESET_N pin is released. After enabling the JTAG interface the halt bit is set automatically to prevent the system from running code after the interface is enabled. To make the CPU run again set halt to zero using the HALT command.. JTAG operation when RESET_N is pulled low is not possible.
PAGE 696
UC3D of TCK. In order to remain in the Shift-DR state, the TMS input must be held low. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state.
PAGE 697
UC3D which is linked to the JTAG through a bus master module, which also handles synchronization between the TCK and SAB clocks. For more information about the SAB and a list of SAB slaves see the Service Access Bus chapter. 31.5.11.1 SAB Address Mode The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address on the bus.
PAGE 698
UC3D continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting data, you must be prepared that the data shift may also report busy. • During Shift-DR of an address: The new address is ignored. The SAB stays in address mode, so no data must be shifted. Repeat the address until the busy bit clears. • During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat scanning until the busy bit clears.
PAGE 699
UC3D • Perform a CHIP_ERASE to clear the security bit. NOTE: This will erase all the contents of the non-volatile memory. 31.6 JTAG Instruction Summary The implemented JTAG instructions in the 32-bit AVR are shown in the table below. Table 31-38. JTAG Instruction Summary Instruction OPCODE Instruction Description 0x01 IDCODE Select the 32-bit Device Identification register as data register. 0x02 SAMPLE_PRELOAD Take a snapshot of external pin values without affecting system operation.
PAGE 700
UC3D Note that the security bit will read as programmed and block these instructions also if the Flash Controller is statically reset. Other security mechanisms can also restrict these functions. If such mechanisms are present they are listed in the SAB address map section. 31.6.1.1 Notation Table 31-40 on page 700 shows bit patterns to be shifted in a format like "peb01". Each character corresponds to one bit, and eight bits are grouped together for readability.
PAGE 701
UC3D Table 31-40. Instruction Description (Continued) 31.6.2 Instruction Description DR Size Shows the number of bits in the data register chain when this instruction is active. Example: 34 bits DR input value Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g., to distinguish between reads and writes.
PAGE 702
UC3D 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan chain. 7. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. Table 31-42. SAMPLE_PRELOAD Details 31.6.2.
PAGE 703
UC3D 31.6.2.4 INTEST This instruction selects the boundary-scan chain as Data Register for testing internal logic in the device. The logic inputs are determined by the boundary-scan chain, and the logic outputs are captured by the boundary-scan chain. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the INTEST instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3.
PAGE 704
UC3D 9. Return to Run-Test/Idle. Table 31-45. CLAMP Details 31.6.2.6 Instructions Details IR input value 00110 (0x06) IR output value p0001 DR Size 1 DR input value x DR output value x BYPASS This instruction selects the 1-bit Bypass Register as Data Register. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3.
PAGE 705
UC3D Starting in Run-Test/Idle, OCD registers are accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the OCD register. 7. Go to Update-DR and re-enter Select-DR Scan. 8.
PAGE 706
UC3D 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 9. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 31-48.
PAGE 707
UC3D The size field is encoded as i Table 31-49. Table 31-49.
PAGE 708
UC3D Table 31-50. MEMORY_SIZED_ACCESS Details (Continued) 31.6.3.4 Instructions Details DR output value (Address phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb DR output value (Data read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb MEMORY_WORD_ACCESS This instruction allows access to the entire Service Access Bus data area.
PAGE 709
UC3D Table 31-51. MEMORY_WORD_ACCESS Details (Continued) 31.6.3.5 Instructions Details DR output value (Address phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb DR output value (Data read phase) xeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb MEMORY_BLOCK_ACCESS This instruction allows access to the entire SAB data area.
PAGE 710
UC3D Table 31-52. MEMORY_BLOCK_ACCESS Details (Continued) Instructions Details DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% transfer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency. 31.6.3.
PAGE 711
UC3D 6. Scan in an 16-bit counter value. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7. 9. Calculate an approximation to the internal clock speed using the elapsed time and the counter value. 10. Return to Run-Test/Idle. The full 16-bit counter value must be provided when starting the synch operation, or the result will be undefined.
PAGE 712
UC3D Table 31-55. AVR_RESET Details (Continued) 31.6.3.9 Instructions Details DR Size Device specific. DR input value Device specific. DR output value Device specific. CHIP_ERASE This instruction allows a programmer to completely erase all nonvolatile memories in a chip. This will also clear any security bits that are set, so the device can be accessed normally. In devices without non-volatile memories this instruction does nothing, and appears to complete immediately.
PAGE 713
UC3D 6. In Shift-DR: Scan in the value 1 to halt the CPU, 0 to start CPU execution. 7. Return to Run-Test/Idle. Table 31-57.
PAGE 714
UC3D 31.6.4 JTAG Data Registers The following device specific registers can be selected as JTAG scan chain depending on the instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly described in the functional description of the relevant instructions. 31.6.4.1 Device Identification Register The Device Identification Register contains a unique identifier for each product.
PAGE 715
UC3D internal logic. Typically, output value, output enable, and input data are all available in the boundary scan chain. The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file available at the Atmel web site. 31.7 NanoTrace and Auxilliary Port NanoTrace and Auxilliary(AUX) Port features have not been implemented in this chip. All references to these concepts are invalid. 31.
PAGE 716
UC3D 32. Electrical Characteristics 32.1 Disclaimer All values in this chapter are preliminary and subject to change without further notice. 32.2 Absolute Maximum Ratings* Table 32-1. Absolute Maximum Ratings Operating temperature .................................... -40°C to +85°C *NOTICE: Storage temperature ...................................... -60°C to +150°C Voltage on input pins (except for 5V pins) with respect to ground .................................................................-0.
PAGE 717
UC3D • Temperature = -40°C to 85°C Table 32-3. 32.
PAGE 718
UC3D Table 32-4. Mode Active Idle Frozen Standby Stop Deepstop Static Power Consumption for Different Operating Modes Conditions Consumption Typ Unit 0.3105xf(MHz) + 0.2707 mA/MHz Same conditions at 48MHz 15.17 mA See Active mode conditions 0.1165xf(MHz) + 0.1457 mA/MHz Same conditions at 48MHz 5.74 mA See Active mode conditions 0.0718xf(MHz) + 0.0903 mA/MHz Same conditions at 48MHz 3.54 mA See Active mode conditions 0.0409xf(MHz) + 0.0935 mA/MHz Same conditions at 48MHz 2.
PAGE 719
UC3D Figure 32-1. Measurement Schematic, External Core Supply VDDANA VDDIO Amp0 VDDIN Internal Voltage Regulator VDDOUT Amp1 32.5.1 VDDCORE Peripheral Power Consumption The values in Table 32-5 are measured values of power consumption under the following conditions. • Operating conditions external core supply (Figure 32-1) – VVDDIN = 3.3V – VVDDCORE = 1.8V, supplied by the internal regulator – Corresponds to the 3.3V + 1.
PAGE 720
UC3D • I/Os are inactive with internal pull-up Consumption idle is the added current consumption when turning the module clock on and the module is uninitialized. Consumption active is the added current consumption when the module clock is turned on and when the module is doing a typical set of operations. Table 32-5. Typical Current Consumption by Peripheral Peripheral ADCIFD Unit 3.6 AST 4.5 AW USART 9.8 CAT 14 EIC 2.3 FREQM 1.1 GLOC 1.3 GPIO 10.6 IISC 4.7 PWMA 5.6 SPI 6.
PAGE 721
UC3D Table 32-6. Symbol IOL Normal I/O Pin Characteristics(1) Parameter Output low-level current Output high-level current IOH Condition Min VVDD = 3.0V VVDD = 3.0V VVDD = 3.0V, load = 10 pF Output frequency(2) FMAX VVDD = 3.0V, load = 30 pF VVDD = 3.0V, load = 10 pF Rise time(2) tRISE VVDD = 3.0V, load = 30 pF VVDD = 3.0V, load = 10 pF Fall time(2) tFALL VVDD = 3.
PAGE 722
UC3D Table 32-7. High-drive I/O Pin Characteristics(1) Symbol Parameter Condition VOH Output high-level voltage VVDD = 3.0V, IOH = 6mA IOL Output low-level current VVDD = 3.0V 16 mA IOH Output high-level current VVDD = 3.0V 16 mA FMAX Output frequency VVDD = 3.0V, load = 10 pF 471 MHz VVDD = 3.0V, load = 30 pF 249 MHz tRISE Rise time, all High-drive I/O pins VVDD = 3.0V, load = 10 pF 0.86 ns VVDD = 3.0V, load = 30 pF 1.70 ns tFALL Fall time VVDD = 3.0V, load = 10 pF 1.
PAGE 723
UC3D 32.7 Oscillator Characteristics 32.7.1 Oscillator 0 (OSC0) Characteristics 32.7.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 32-10. Digital Clock Characteristics Symbol Parameter fCPXIN XIN clock frequency tCPXIN XIN clock duty cycle 32.7.1.
PAGE 724
UC3D Figure 32-2. Oscillator Connection C LE X T XO U T U C 3D Ci CL XIN C LEX T 32.7.2 32KHz Crystal Oscillator (OSC32K) Characteristics 32.7.2.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32. Table 32-12. Digital Clock Characteristics Symbol Parameter fCPXIN XIN32 clock frequency tCPXIN XIN32 clock duty cycle Conditions Min Typ Max 32.
PAGE 725
UC3D 32.7.3 Phase Locked Loop (PLL) Characteristics Table 32-14. Phase Lock Loop Characteristics Symbol Parameter FOUT VCO Output Frequency FIN Input Frequency IPLL Current Consumption tSTARTUP Startup time, from enabling the PLL until the PLL is locked 32.7.4 Conditions Min. Typ. Max.
PAGE 726
UC3D Table 32-18. Flash Characteristics Symbol Parameter TFPP Page programming time TFPE Page erase time TFFP Fuse programming time TFEA Full chip erase time (EA) TFCE JTAG chip erase time (CHIP_ERASE) Conditions Min Typ Max Unit 5 5 fCLK_HSB= 48MHz ms 1 6 fCLK_HSB= 115kHz 310 Table 32-19.
PAGE 727
UC3D Table 32-21. Decoupling Requirements Symbol Parameter CIN2 Typ Techno. Units Input regulator capacitor 2 4.7 X7R nF COUT1 Output regulator capacitor 1 470 NPO nF COUT2 Output regulator capacitor 2 2.2 X7R µF 32.9.2 Condition ADC Characteristics Table 32-22. Channel Conversion Time and ADC Clock Parameter Conditions Min. Typ. Max.
PAGE 728
UC3D Table 32-25. Transfer Characteristics in 8-bit mode Parameter Conditions Differential Non-linearity Min. Typ. Max. Unit ADC Clock = 5 MHz 0.3 0.5 LSB ADC Clock = 8 MHz 0.5 1.0 LSB Offset Error ADC Clock = 5 MHz -0.5 0.5 LSB Gain Error ADC Clock = 5 MHz -0.5 0.5 LSB Max. Unit 3 LSB Table 32-26. Transfer Characteristics in 10-bit mode Parameter Conditions Min. Typ. Resolution 10 Bit Absolute Accuracy ADC Clock = 5 MHz Integral Non-linearity ADC Clock = 5 MHz 1.
PAGE 729
UC3D 32.9.4 Reset Sequence Table 32-29. Electrical Characteristics Symbol Parameter Conditions Min. VDDRR VDDCORE rise rate to ensure poweron-reset 2.5 VDDFR VDDCORE fall rate to ensure poweron-reset 0.01 VPOR+ Rising threshold voltage: voltage up to which device is kept under reset by POR on rising VDDCORE Rising VDDCORE: VRESTART -> VPOR+ 1.4 VPOR- Falling threshold voltage: voltage when POR resets device on falling VDDCORE Falling VDDCORE: 1.8V -> VPOR+ 1.
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UC3D Figure 32-4. MCU Cold Start-Up RESET_N Externally Driven VDDCORE VPOR- VPOR+ VRESTART RESET_N Internal POR Reset TPOR TRST TSSU1 Internal MCU Reset Figure 32-5. MCU Hot Start-Up VDDCORE RESET_N BOD Reset WDT Reset TSSU2 Internal MCU Reset In dual supply configuration, the power up sequence must be carefully managed to ensure a safe startup of the device in all conditions.
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UC3D Figure 32-6. Dual Supply Configuration V D D IO m in 2. 5 V V DD /m R sm R ini m um V D D IO V p or+ m in VDDCORE < 50 0 u s TSSU1 TRST Interna l POR (a ctive lo w ) F irst ins tructio n fe tch ed in fla sh 32.9.5 RESET_N Characteristics Table 32-30. RESET_N Waveform Parameters Symbol Parameter Conditions tRESET RESET_N minimum pulse width Min. Typ. Max. 10 Unit ns 32.10 USB Transceiver Characteristics 32.10.
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UC3D 33. Mechanical Characteristics 33.1 33.1.1 Thermal Considerations Thermal Data Table 33-1 summarizes the thermal resistance data depending on the package. Table 33-1. 33.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP48 65.1 θJC Junction-to-case thermal resistance TQFP48 23.4 θJA Junction-to-ambient thermal resistance QFN48 29.2 θJC Junction-to-case thermal resistance QFN48 2.
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UC3D 33.2 Package Drawings Figure 33-1. TQFP-64 package drawing Table 33-2. Device and Package Maximum Weight Weight Table 33-3. 300 mg Package Characteristics Moisture Sensitivity Level Table 33-4.
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UC3D Figure 33-2. TQFP-48 package drawing Table 33-5. Device and Package Maximum Weight Weight Table 33-6. 100 mg Package Characteristics Moisture Sensitivity Level Table 33-7.
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UC3D Figure 33-3. QFN-48 Package Drawing Table 33-8. Device and Package Maximum Weight Weight Table 33-9. 100 mg Package Characteristics Moisture Sensitivity Level Jedec J-STD-20D-MSL3 Table 33-10.
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UC3D Figure 33-4. QFN-64 package drawing Table 33-11. Device and Package Maximum Weight Weight 200 mg Table 33-12. Package Characteristics Moisture Sensitivity Level Jedec J-STD-20D-MSL3 Table 33-13.
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UC3D 33.3 Soldering Profile Table 33-14 gives the recommended soldering profile from J-STD-20. Table 33-14.
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UC3D 34. Ordering Information Table 34-1.
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UC3D 35. Errata 35.1 Rev. C 35.1.1 SPI 1. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 2. PCS field in receive data register is inaccurate The PCS field in the SPI_RDR register does not accurately indicate from which slave the received data is read. Fix/Workaround None. 3. SPI data transfer hangs with CSR0.
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UC3D 35.1.2 TWIS 1. Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. 35.1.3 PWMA 1. The SR.READY bit cannot be cleared by writing to SCR.
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UC3D 4. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 5.
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UC3D 35.3 35.3.1 Rev. A GPIO 1. Clearing Interrupt flags can mask other interrupts When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. Fix/Workaround Read the PVR register of the port before and after clearing the interrupt to see if any pin change has happened while clearing the interrupt. If any change occurred in the PVR between the reads, they must be treated as an interrupt. 35.3.2 Power Manager 1.
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UC3D Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 8. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK.
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UC3D 35.3.3 Timer Counter 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 35.3.4 TWIS 1.
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UC3D 36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 Rev. A – 11/2009 1. 36.2 Rev. B – 04/2011 1. 36.3 Minor. Rev. C – 07/2011 1. 36.4 Initial revision. Final revision. Rev. D – 11/2011 1. 2. Adding errata for silicon Revision C .
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UC3D Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 5 6 7 8 2.1 Block Diagram ...................................................................................................5 2.
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UC3D 9 8.7 Security Bit ......................................................................................................46 8.8 User Interface ..................................................................................................47 8.9 Fuse Settings ...................................................................................................57 8.10 Bootloader Configuration .................................................................................58 8.
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UC3D 12.6 Functional Description ...................................................................................107 12.7 User Interface ................................................................................................114 12.8 Module Configuration ....................................................................................136 13 System Control Interface (SCIF) ......................................................... 137 13.1 Features ........................................
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UC3D 16.8 Module Configuration ....................................................................................237 17 Frequency Meter (FREQM) .................................................................. 238 17.1 Features ........................................................................................................238 17.2 Overview ........................................................................................................238 17.3 Block Diagram .........................
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UC3D 20.7 User Interface ................................................................................................355 20.8 Module Configuration ....................................................................................374 21 Serial Peripheral Interface (SPI) ......................................................... 375 21.1 Features ........................................................................................................375 21.2 Overview ...............................
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UC3D 24.2 Overview ........................................................................................................474 24.3 List of Abbreviations ......................................................................................475 24.4 Block Diagram ...............................................................................................475 24.5 Application Block Diagram .............................................................................475 24.6 I/O Lines Description ..
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UC3D 27.8 Module Configuration ....................................................................................605 28 ADC Interface (ADCIFD) ...................................................................... 606 28.1 Feature ..........................................................................................................606 28.2 Overview ........................................................................................................606 28.3 Block diagram .....................
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UC3D 31.7 NanoTrace and Auxilliary Port .......................................................................715 31.8 Module Configuration ....................................................................................715 32 Electrical Characteristics .................................................................... 716 32.1 Disclaimer ......................................................................................................716 32.2 Absolute Maximum Ratings* ....................
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UC3D 754 32133D–11/2011
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Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.