Datasheet

32142DS–06/2013

ATUC64/128/256L3/4U

4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and

NCPHA=0

When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one

(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,

then an additional pulse will be generated on SCK.

Fix/Workaround

When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1

if CSRn.CPOL=1 and CSRn.NCPHA=0.

5. SPI mode fault detection enable causes incorrect behavior

When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate

properly.

Fix/Workaround

Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.

6. SPI RDR.PCS is not correct

The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not

correctly indicate the value on the NPCS pins at the end of a transfer.

Fix/Workaround

Do not use the PCS field of the SPI RDR.

6.2.4 TWI

1. TWIS may not wake the device from sleep mode

If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condi-

tion, the CPU may not wake upon a TWIS address match. The request is NACKed.

Fix/Workaround

When using the TWI address match to wake the device from sleep, do not switch to sleep

modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the

TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus

events.

2. SMBALERT bit may be set after reset

The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after

system reset.

Fix/Workaround

After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.

3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus

When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-

ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to

attempt to continue transmitting data, thus locking up the bus.

Fix/Workaround

Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been

set.

6.2.5 PWMA

1. The SR.READY bit cannot be cleared by writing to SCR.READY

The Ready bit in the Status Register will not be cleared when writing a one to the corre-

sponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is

set.

Fix/Workaround