Datasheet

17
32142DS–06/2013
ATUC64/128/256L3/4U
Note: 1. ADCIFB: AD3 does not exist.
B0 Channel 0 Line B I/O
B1 Channel 1 Line B I/O
B2 Channel 2 Line B I/O
CLK0 Channel 0 External Clock Input Input
CLK1 Channel 1 External Clock Input Input
CLK2 Channel 2 External Clock Input Input
Two-wire Interface - TWIMS0, TWIMS1
TWALM SMBus SMBALERT I/O Low
TWCK Two-wire Serial Clock I/O
TWD Two-wire Serial Data I/O
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3
CLK Clock I/O
CTS Clear To Send Input Low
RTS Request To Send Output Low
RXD Receive Data Input
TXD Transmit Data Output
Table 3-7. Signal Descriptions List
Table 3-8. Signal Description List, Continued
Signal Name Function Type
Active
Level Comments
Power
VDDCORE Core Power Supply / Voltage Regulator Output
Power
Input/Output
1.62V to 1.98V
VDDIO I/O Power Supply Power Input
1.62V to 3.6V. VDDIO should
always be equal to or lower than
VDDIN.
VDDANA Analog Power Supply Power Input 1.62V to 1.98V
ADVREFP Analog Reference Voltage Power Input 1.62V to 1.98V
VDDIN Voltage Regulator Input Power Input 1.62V to 3.6V
(1)
GNDANA Analog Ground Ground
GND Ground Ground
Auxiliary Port - AUX
MCKO Trace Data Output Clock Output
MDO5 - MDO0 Trace Data Output Output