Features • High Performance, Low Power AVR 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85) • Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85) • Endurance: 100,000 Write/Erase Cycles –
1. Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 SOIC (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) 2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture.
ATtiny25/45/85 2.1 Block Diagram Figure 2-1. Block Diagram 8-BIT DATABUS CALIBRATED INTERNAL OSCILLATOR PROGRAM COUNTER STACK POINTER PROGRAM FLASH SRAM WATCHDOG TIMER TIMING AND CONTROL VCC MCU CONTROL REGISTER MCU STATUS REGISTER GND INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES GENERAL PURPOSE REGISTERS TIMER/ COUNTER0 X Y Z TIMER/ COUNTER1 ALU UNIVERSAL SERIAL INTERFACE STATUS REGISTER INTERRUPT UNIT PROGRAMMING LOGIC DATA EEPROM DATA REGISTER PORT B DATA DIR. REG.
The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes.
ATtiny25/45/85 2.3 2.3.1 Pin Descriptions VCC Supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
4.2 Architectural Overview Figure 4-1.
ATtiny25/45/85 The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions are 16-bits wide. There are also 32-bit instructions.
• Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
ATtiny25/45/85 4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
4.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. Figure 4-3.
ATtiny25/45/85 4.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag.
ATtiny25/45/85 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 4.8.
Figure 5-1. Program Memory Map Program Memory 0x0000 0x03FF/0x07FF 5.2 SRAM Data Memory Figure 5-2 shows how the ATtiny25/45/85 SRAM Memory is organized. The lower 224/352/607 Data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O memory, and the last 128/256/512 locations address the internal data SRAM.
ATtiny25/45/85 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3. Figure 5-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 5.3 Next Instruction EEPROM Data Memory The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory.
5.3.2 EEPROM Address Register High – EEARH Bit 7 6 5 4 3 2 1 0 - - - - - - - EEAR8 Read/Write R R R R R R R R/W Initial Value X X X X X X X X EEARH • Bit 7..1 – Res6..0: Reserved Bits These bits are reserved for future use and will always read as 0 in ATtiny25/45/85. • Bits 0 – EEAR8: EEPROM Address The EEPROM Address Register – EEARH – specifies the high EEPROM address in the 128/256/512 bytes EEPROM space.
ATtiny25/45/85 • Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny25/45/85 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations.
5.3.6 Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEAR Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 20-1.
ATtiny25/45/85 Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode ldi r16, (0<
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATtiny25/45/85 5.4 I/O Memory The I/O space definition of the ATtiny25/45/85 is shown in “Register Summary” on page 182. All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
6.1.1 CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 6.1.2 I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter.
ATtiny25/45/85 Figure 6-2. PCK Clocking System OSCCAL PLLE PLLCK & CKSEL FUSES CLKPS3..0 PLOCK Lock Detector RC OSCILLATOR 8.0 MHz / 6.4 MHz PCK PLL 8x / 4x 64 / 25.6 MHz DIVIDE BY 4 XTAL1 XTAL2 6.2 System Clock Prescaler SYSTEM CLOCK OSCILLATORS Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6-1.
Table 6-2. 6.3 Number of Watchdog Oscillator Cycles Typ Time-out Number of Cycles 4 ms 512 64 ms 8K (8,192) Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at 8 MHz with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer.
ATtiny25/45/85 Table 6-4. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..
6.6 Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides an 8.0 MHz clock. The frequency is the nominal value at 3V and 25°C. If the frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 during start-up. See “System Clock Prescaler” on page 29. for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6-6.
ATtiny25/45/85 The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80. The CAL6..0 bits are used to tune the frequency within the selected range.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page 29 for details. 6.7.1 High Frequency PLL Clock - PLLCLK There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source.
ATtiny25/45/85 6.9 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not be output during reset and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of eight at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting.
ATtiny25/45/85 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
Table 7-1. Sleep Mode Select SM1 SM0 Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Stand-by mode • Bit 2 – BODSE: BOD Sleep Enable BOD disable functionality is available in some devices, only. See “Limitations” on page 33. The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is controlled by a timed sequence.
ATtiny25/45/85 Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 58 for details.. Table 7-2.
• Bit 2- PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 1 - PRUSI: Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation. • Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC.
ATtiny25/45/85 7.7.5 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 41 for details on how to configure the Watchdog Timer. 7.7.
Figure 8-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[1:0] SUT[1:0] 8.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 8-1. The POR is activated whenever VCC is below the detection level.
ATtiny25/45/85 Figure 8-2. MCU Start-up, RESET Tied to VCC V CCRR VCC VPORMAX VPORMIN RESET VRST tTOUT TIME-OUT INTERNAL RESET Figure 8-3. VCC MCU Start-up, RESET Extended Externally VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET Table 8-1. Symbol Power On Reset Specifications Parameter Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling) Typ Max Units 1.1 1.4 1.7 V 0.8 1.3 1.6 V 0.4 V VPORMAX VCC Max.
Figure 8-4. External Reset During Operation CC 8.5 Brown-out Detection ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 8-2.
ATtiny25/45/85 When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure 8-5), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 8-5), the delay counter starts the MCU after the Time-out period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in Table 8-1. Figure 8-5.
8.7 MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs.
ATtiny25/45/85 ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Table 8-4. Symbol 8.9 Internal Voltage Reference Characteristics Parameter Condition Min Typ Max Units VCC = 1.1V / 2.7V, TA = 25°C 1.0 1.1 1.2 V 70 µs VBG Bandgap reference voltage tBG Bandgap reference start-up time VCC = 2.
8.9.1 Watchdog Timer Control Register – WDTCR Bit 7 6 5 4 3 2 1 0 WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCR • Bit 7 – WDIF: Watchdog Timeout Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
ATtiny25/45/85 In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCU Status Register – MCUSR” on page 40 for description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny25/45/85 8.10.2 Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2.
If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATtiny25/45/85 Figure 10-1. I/O Pin Equivalent Schematic Rpu Logic Pxn Cpin See Figure "General Digital I/O" for Details All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn.
Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 10.2.1 PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WRx: RRx: RPx: WPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
ATtiny25/45/85 10.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
ATtiny25/45/85 Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
10.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATtiny25/45/85 Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2.
10.3.1 MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 48 for more details about this feature. 10.3.
ATtiny25/45/85 • Port B, Bit 4- XTAL2/CLKO/ADC2/OC1B/PCINT4 XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator or External clock as a Chip clock sources, PB4 serves as an ordinary I/O pin. CLKO: The devided system clock can be output on the pin PB4.
OC0B: Output Compare Match output. The PB1 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function. OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin is also the output pin for the PWM mode timer function.
ATtiny25/45/85 Table 10-4 and Table 10-5 relate the alternate functions of Port B to the overriding signals shown in Figure 10-5 on page 52. Table 10-4. Overriding Signals for Alternate Functions in PB5..
10.4 10.4.1 Register Description for I/O-Ports Port B Data Register – PORTB Bit 10.4.2 7 6 5 4 3 2 1 0 – – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Port B Data Direction Register – DDRB Bit 10.4.
ATtiny25/45/85 11.1 MCU Control Register – MCUCR The External Interrupt Control Register A contains control bits for interrupt sense control.
11.3 General Interrupt Flag Register – GIFR Bit 7 6 5 4 3 2 1 – INTF0 PCIF – – – – 0 – Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR • Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
ATtiny25/45/85 12. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: • • • • • • • 12.
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 63. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. 12.1.
ATtiny25/45/85 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
Figure 12-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
ATtiny25/45/85 12.4.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 72. 12.5.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
ATtiny25/45/85 The timing diagram for the CTC mode is shown in Figure 12-5. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 12-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag.
This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-6.
ATtiny25/45/85 Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM.
ATtiny25/45/85 Figure 12-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 12-9 shows the same timing data, but with the prescaler enabled. Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 12-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 12-10.
Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 12.8 8-bit Timer/Counter Register Description 12.8.
ATtiny25/45/85 Table 12-2. Compare Output Mode, Fast PWM Mode(1) COM01 COM00 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match, set OC0A at TOP 1 1 Set OC0A on Compare Match, clear OC0A at TOP Note: Description 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 67 for more details.
Table 12-2 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode. Table 12-5. Compare Output Mode, Fast PWM Mode(1) COM01 COM00 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match, set OC0B at TOP 1 1 Set OC0B on Compare Match, clear OC0B at TOP Note: Description 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP.
ATtiny25/45/85 Table 12-7. Waveform Generation Mode Bit Description Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on(1)(2) Mode WGM2 WGM1 WGM0 0 0 0 0 Normal 0xFF Immediate MAX 1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF TOP MAX 4 1 0 0 Reserved – – – 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved – – – 7 1 1 1 Fast PWM OCRA TOP TOP Notes: 1.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “Timer/Counter Control Register A – TCCR0A” on page 72. • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter.
ATtiny25/45/85 12.8.5 Output Compare Register B – OCR0B Bit 7 6 5 4 3 2 1 0 OCR0B[7:0] OCR0B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 12.8.
• Bit 4– OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
ATtiny25/45/85 13.2 External Clock Source An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O).
Figure 13-2. Prescaler for Timer/Counter0 clk I/O Clear PSR10 T0 Synchronization clkT0 Note: 13.2.1 1. The synchronization logic on the input pins (T0) is shown in Figure 13-1.
ATtiny25/45/85 14. Counter and Compare Units Figure 14-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchronous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base. The PCKE bit from the PLLCSR register enables the asynchronous mode when it is set (‘1’). Figure 14-1.
Figure 14-2. Timer/Counter 1 Synchronization Register Block Diagram.
ATtiny25/45/85 Figure 14-3. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE T/C1 COMPARE FLOW IRQ MATCH A IRQ MATCH B IRQ OC1A (PB1) OC1B (PB4) OC1A (PB0) DEAD TIME GENERATOR PSR1 FOC1B FOC1A COM1B0 PWM1B GLOBAL T/C CONTROL REGISTER (GTCCR) COM1B1 CS10 CS11 CS12 CS13 COM1A0 COM1A1 CTC1 TOV1 T/C CONTROL REGISTER 1 (TCCR1) PWM1A TOV1 TOV0 OCF1B OCF1A OCF1A TIMER INT. FLAG REGISTER (TIFR) OCF1B TOIE1 TOIE0 OCIE1B OCIE1A DEAD TIME GENERATOR TIMER INT.
14.1.1 Timer/Counter1 Control Register - TCCR1 Bit 7 6 5 4 3 2 1 0 $30 ($50) CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1 • Bit 7- CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.
ATtiny25/45/85 Table 14-2. Timer/Counter1 Prescale Select (Continued) Asynchronous Clocking Mode Synchronous Clocking Mode 1 PCK/64 CK/64 0 0 PCK/128 CK/128 0 0 1 PCK/256 CK/256 1 0 1 0 PCK/512 CK/512 1 0 1 1 PCK/1024 CK/1024 1 1 0 0 PCK/2048 CK/2048 1 1 0 1 PCK/4096 CK/4096 1 1 1 0 PCK/8192 CK/8192 1 1 1 1 PCK/16384 CK/16384 CS13 CS12 CS11 CS10 0 1 1 1 0 1 The Stop condition provides a Timer Enable/Disable function. 14.1.
• Bit 3- FOC1B: Force Output Compare Match 1B Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value.
ATtiny25/45/85 14.1.5 Timer/Counter1 Output Compare RegisterB - OCR1B Bit 7 6 5 4 3 2 1 0 $2D ($4D) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1B The output compare register B is an 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1.
• Bit 4– OCIE0A: Timer/Counter Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0A bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.
ATtiny25/45/85 In PWM mode (either PWM1A=1 or PWM1B=1) the bit TOV1 is set (one) when compare match occurs between Timer/Counter1 and data value in OCR1C - Output Compare Register 1C. Clearing the Timer/Counter1 with the bit CTC1 does not generate an overflow. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.
14.1.11 Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the PB1(OC1A) and PB3(OC1B) pins and inverted outputs on pins PB0(OC1A) and PB2(OC1B). As default non-overlapping times for complementary output pairs are zero, but they can be inserted using a Dead Time Generator (see description on page 100). Figure 14-4.
ATtiny25/45/85 Figure 14-5. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value PWM Output OC1x Synchronized OC1x Latch Compare Value changes Counter Value Compare Value PWM Output OC1x Glitch Unsynchronized OC1x Latch During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B.
Resolution shows how many bit is required to express the value in the OCR1C register. It is calculated by following equation ResolutionPWM = log2(OCR1C + 1). Table 14-6. 92 Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency Clock Selection CS13..CS10 OCR1C RESOLUTION 20 kHz PCK/16 0101 199 7.6 30 kHz PCK/16 0101 132 7.1 40 kHz PCK/8 0100 199 7.6 50 kHz PCK/8 0100 159 7.3 60 kHz PCK/8 0100 132 7.1 70 kHz PCK/4 0011 228 7.
ATtiny25/45/85 15. Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B).
The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can have different dead time periods. The dead time is adjusted as the number of prescaled dead time generator clock cycles. Figure 15-3.
ATtiny25/45/85 15.2 Timer/Counter1 Dead Time A - DT1A Bit 7 6 5 4 3 2 1 0 DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 $25 ($45) DT1A The dead time value register A is an 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields, DT1AH3..0 and DT1AL3..0, one for each complementary output.
16. Universal Serial Interface – USI The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. The main features of the USI are: • • • • • • 16.
ATtiny25/45/85 This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software.
Figure 16-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 16-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
ATtiny25/45/85 rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register.
16.2.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
ATtiny25/45/85 Figure 16-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER Figure 16-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used.
Referring to the timing diagram (Figure 16-5.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the Data Direction Register bit must be set to one for the output to be enabled. The slave device’s start detector logic (Figure 16-6.
ATtiny25/45/85 16.3 Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. 16.3.1 Half-duplex Asynchronous Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only. 16.3.2 4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt.
16.4.2 USI Buffer Register – USIBR Bit 7 6 5 4 3 2 1 MSB 0 LSB Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 USIBR The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is completed, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer can be accessed when the CPU reads the received data.
ATtiny25/45/85 The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1).
Table 16-1. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
ATtiny25/45/85 Table 16-2 shows the relationship between the USICS1..0 and USICLK setting and clock source used for the Shift Register and the 4-bit counter. Table 16-2. Relations between the USICS1..
17. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 17-1.
ATtiny25/45/85 This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set an internal 1.1V / 2.56V reference voltage replaces the positive input to the Analog Comparator. The selection of the internal voltage reference is done by writing the REFS2..
17.3 Analog Comparator Multiplexed Input It is possible to select any of the ADC3..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 17-2.
ATtiny25/45/85 18. Analog to Digital Converter 18.1 Features • • • • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Two differential input channels with selectable gain Temperature sensor input channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.1V / 2.
Figure 18-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] AREF INTERNAL 1.1V/2.56V REFERENCE PRESCALER START CONVERSION LOGIC TEMPERATURE SENSOR SAMPLE & HOLD COMPARATOR 10-BIT DAC ADC4 ADC3 ADC2 ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADSC ADATE ADEN ADLAR MUX1 MUX0 MUX DECODER CHANNEL SELECTION VCC 0 ADC DATA REGISTER (ADCH/ADCL) TRIGGER SELECT GAIN SELECTION REFS2..0 BIN IPR 15 ADC CTRL.
ATtiny25/45/85 If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. This figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW. The on-chip temperature sensor is selected by writing the code “1111” to the MUX3..
Figure 18-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
ATtiny25/45/85 The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
Figure 18-5. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 9 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 18-6.
ATtiny25/45/85 Table 18-1. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Total Conversion Time (Cycles) First conversion 13.5 25 Normal conversions 1.5 13 2 13.5 Condition Auto Triggered conversions 18.5 Changing Channel or Reference Selection The MUX3..0 and REFS2..0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access.
18.5.2 18.6 ADC Voltage Reference The voltage reference for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V / 2.56V voltage reference, or external AREF pin. The first ADC conversion result after switching voltage reference source may be inaccurate, and the user is advised to discard this result.
ATtiny25/45/85 Figure 18-8. Analog Input Circuitry IIH ADCn 1..100 kohm CS/H= 14 pF IIL VCC/2 18.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible.
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 18-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 18-11.
ATtiny25/45/85 Figure 18-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference (see Table 18-3 on page 123 and Table 18-4 on page 124). The voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 1x or 20x. 18.7.
ATtiny25/45/85 The values described in Table 51 are typical values. However, due to the process variation the temperature sensor output voltage varies from one chip to another. To be capable of achieving more accurate results the temperature measurement can be calibrated in the application software. The software calibration requires that a calibration value is measured and stored in a register or EEPROM for each chip, as a part of the production test.
• Bits 3:0 – MUX3:0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. In case of differential input (ADC0 - ADC1 or ADC2 - ADC3), gain selection is also made with these bits. Selecting ADC2 or ADC0 as both inputs to the differential gain stage enables offset measurements. Selecting the single-ended channel ADC4 enables the temperature sensor. Refer to Table 18-4 for details.
ATtiny25/45/85 The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect.
18.7.7 18.7.7.1 The ADC Data Register – ADCL and ADCH ADLAR = 0 Bit Read/Write Initial Value 18.7.7.
ATtiny25/45/85 • Bit 5 – IPR: Input Polarity Mode The Input Polarity mode allows software selectable differential input pairs and full 10 bit ADC resolution, in the unipolar input mode, assuming a pre-determined input polarity. If the input polarity is not known it is actually possible to determine the polarity first by using the bipolar input mode (with 9 bit resolution + 1 sign bit ADC measurement).
19. debugWIRE On-chip Debug System 19.1 Features • • • • • • • • • • 19.
ATtiny25/45/85 When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 19.
20. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
ATtiny25/45/85 20.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • The CPU is halted during the Page Write operation. 20.4 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
20.4.1 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations. Bit 7 6 5 4 3 2 1 0 – – – CTPB RFLB PGWRT PGERS SPMEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCSR • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
ATtiny25/45/85 20.4.2 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 20.4.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used.
ATtiny25/45/85 Table 21-2. Lock Bit Protection Modes(1)(2) Memory Lock Bits Protection Type LB Mode LB2 LB1 1 1 1 No memory lock features enabled. 0 Further programming of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode. The Fuse bits are locked in both Serial and High-voltage Programming mode.(1) debugWire is disabled. 0 Further programming and verification of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode.
Table 21-4. Fuse High Byte Fuse High Byte Description Default Value 2 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL1 1 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL0(5) 0 Brown-out Detector trigger level 1 (unprogrammed) (5) (5) BODLEVEL2 Notes: Bit No 1. See “Alternate Functions of Port B” on page 54 for description of RSTDISBL and DWEN Fuses. 2. DWEN must be unprogrammed when Lock Bit security is required. See “Program And Data Memory Lock Bits” on page 134.
ATtiny25/45/85 21.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and High-voltage Programming mode, also when the device is locked. The three bytes reside in a separate address space. 21.3.1 ATtiny25 Signature Bytes 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x91 (indicates 2 KB Flash memory). 3. 0x002: 0x08 (indicates ATtiny25 device when 0x001 is 0x91). 21.3.2 ATtiny45 Signature Bytes 1.
21.6 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 21-8 on page 138, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.
ATtiny25/45/85 To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 21-10): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2.
Table 21-9. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 4.0 ms tWD_FUSE 4.5 ms Figure 21-2. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 21-10.
ATtiny25/45/85 Table 21-10. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page. 1100 0010 00xx xxxx xxbb bb00 xxxx xxxx 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 21-1 on page 134 for details. 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits.
21.6.2 Serial Programming Characteristics Figure 21-3. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 21-11. Serial Programming Characteristics, TA = -40°C to 125°C, VCC = 2.7 - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (ATtiny25/45/85V) Oscillator Period (ATtiny25/45/85V) tCLCL 1/tCLCL Oscillator Period (ATtiny25/45/85L, VCC = 2.7 5.
ATtiny25/45/85 Figure 21-4. High-voltage Serial Programming Table 21-12. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode Pin Name I/O Function SDI PB0 I Serial Data Input SII PB1 I Serial Instruction Input SDO PB2 O Serial Data Output SCI PB3 I Serial Clock Input (min. 220ns period) Table 21-13. High-voltage Serial Programming Characteristics TA = 25°C ±10%, VCC = 5.
21.8 High-voltage Serial Programming Algorithm Sequence To program and verify the ATtiny25/45/85 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 21-16): 21.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET pin to “0” and toggle SCI at least six times. 3.
ATtiny25/45/85 21.8.4 Programming the Flash The Flash is organized in pages, see Table 21-10 on page 140. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: 1. Load Command “Write Flash” (see Table 21-16). 2. Load Flash Page Buffer. 3. Load Flash High Address and Program Page. Wait after Instr.
21.8.5 Programming the EEPROM The EEPROM is organized in pages, see Table 21-11 on page 142. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 21-16): 1. Load Command “Write EEPROM”. 2. Load EEPROM Page Buffer. 3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Programming” cycle to finish. 4.
ATtiny25/45/85 Table 21-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 Instruction Format Instruction Chip Erase Load “Write Flash” Command Load Flash Page Buffer Instr.1/5 Instr.2/6 Instr.
Table 21-16.
ATtiny25/45/85 21.9 High-voltage Serial Programming Characteristics Figure 21-7. High-voltage Serial Programming Timing CC CK Table 21-17. High-voltage Serial Programming Characteristics TA = 25°C ±10%, VCC = 5.
22. Electrical Characteristics 22.1 Absolute Maximum Ratings* Operating Temperature.................................. -40°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATtiny25/45/85 DC Characteristics TA = -40°C to 125°C, VCC = 2.7V to 5.5V (unless otherwise noted)(1) . Table 22-1. Symbol Parameter Power Supply Current ICC(6) Power-down mode(7) Notes: Typ. Max.(3) Units Active 4MHz, VCC = 3V 1.25 3 mA Active 8MHz, VCC = 5V 5 10 mA Active 16MHz, VCC = 5V 10 15 mA Idle 4MHz, VCC = 3V 0.4 0.5 mA Idle 8MHz, VCC = 5V 1.2 2 mA Idle 16MHz, VCC = 5V 2.
22.3 External Clock Drive Table 22-2. External Clock Drive(1). PRELIMINARY VCC = 4.5 5.5V VCC = 2.7 - 5.5V Min. Max. Min. Max. Units 0 8 0 16 MHz Symbol Parameter 1/tCLCL Clock Frequency tCLCL Clock Period 100 50 ns tCHCX High Time 40 20 ns tCLCX Low Time 40 20 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.5 µs ΔtCLCL Change in period from one clock cycle to the next 2 2 % Note: 1.
ATtiny25/45/85 22.4 ADC Characteristics – Preliminary Data ADC Characteristics, Single Ended Channels. -40°C - 125°C. (1). PRELIMINARY Table 22-3. Symbol Parameter Resolution Single Ended Conversion Max(1) Units 10 Bits LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
22.5 Calibrated RC Oscillator Accuracy Table 22-4. Calibration Accuracy of Internal RC Oscillator Factory Calibration User Calibration Frequency Vcc Temperature Calibration Accuracy 8.0 MHz 3V 25°C ±1% 7.3 - 8.1 MHz 2.7V - 5.5V -40°C - +125°C ±14% 23. Typical Characteristics The data contained in this section is extracted from preliminary silicon characterization and will be updated upon final characterization. The following charts show typical behavior.
ATtiny25/45/85 23.1 Active Supply Current Figure 23-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.040 5.5 V 0.035 5.0 V 0.030 4.5 V 4.0 V 0.025 0.020 3.3 V 2.7 V 0.015 0.010 0.005 0.000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que nc y (MHz ) Figure 23-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 - 20MHz 14 5.5 V 12 5.0 V ICC (mA) 10 4.5 V 8 4.0 V 6 3.3 V 4 2.
Figure 23-3. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 128 KHz 0.25 125 85 25 -40 ICC(mA) 0.2 ˚C ˚C ˚C ˚C 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 1 MHz 1.8 1.6 125 85 25 -40 1.4 ICC (mA) 1.2 ˚C ˚C ˚C ˚C 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny25/45/85 Figure 23-5. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE S UP P LY CURRENT vs . V CC INTERNAL RC OSCILLATOR, 8 MHz 8 7 125 85 25 -40 ICC (mA) 6 ˚C ˚C ˚C ˚C 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 23.2 Idle Supply Current Figure 23-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz 0.25 5.5 V 0.2 5.0 V Idle (mA) 4.5 V 4.0 V 0.15 3.3 V 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.
Figure 23-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE S UP P LY CURRENT vs . FREQUENCY 1 - 20MHz Idle (mA) 4 3.5 5.5 V 3 5.0 V 2.5 4.5 V 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 23-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 128 KHz 0.25 125 85 25 -40 0.2 ˚C ˚C ˚C ˚C ICC 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny25/45/85 Figure 23-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 1 MHz 0.6 0.5 Idle (mA) 0.4 125 85 25 -40 ˚C ˚C ˚C ˚C 125 85 25 -40 ˚C ˚C ˚C ˚C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 Idle (mA) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.
23.2.1 Using the Power Reduction Register The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See “Power Reduction Register” on page 33 for details. Table 23-1.
ATtiny25/45/85 23.3 Power-Down Supply Current Figure 23-11. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER DISABLED 4 125 ˚C 3.5 3 ICC (uA) 2.5 2 1.5 1 85 ˚C 0.5 -40 ˚C 25 ˚C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-12. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER ENABLED 12 10 125 ˚C -40 ˚C 25 ˚C 85 ˚C ICC (uA) 8 6 4 2 0 1.5 2 2.
23.4 Pin Pull-up Figure 23-13. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 1.8V 60 50 IOP (uA) 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -40 25 85 2 125 ˚C ˚C ˚C ˚C V OP (V) Figure 23-14. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 2.7V 90 80 70 IOP (uA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATtiny25/45/85 Figure 23-15. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 5.0V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 5.0V 160 140 120 IOP (uA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 125 ˚C 85 ˚C 25 ˚C 5 -40 ˚C V OP (V) Figure 23-16. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 1.8V 40 35 IRE S E T (uA) 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.
Figure 23-17. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 2.7V 70 60 IRE S E T (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 125 85 25 -40 ˚C ˚C ˚C ˚C V RES ET (V) Figure 23-18. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5.0V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 5.
ATtiny25/45/85 23.5 Pin Driver Strength Figure 23-19. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) I/O P IN S INK CURRENT vs . OUTP UT VOLTAGE V CC = 1.8V 12 -40 ˚C 10 25 ˚C 85 ˚C 125 ˚C IOL (mA) 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 V OL (V) Figure 23-20. I/O Pin Source Current vs. Output Voltage (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT Vc c = 3.0V 1.2 125 1 85 V OL (V) 0.8 25 0.6 -40 0.4 0.
Figure 23-21. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT Vc c = 5.0V 0.7 125 0.6 85 V OL (V) 0.5 25 -40 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (V) Figure 23-22. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) I/O P IN S OURCE CURRENT vs . OUTP UT VOLTAGE V CC = 1.8V 9 8 25 ˚C 7 IOH (mA) 6 -40 ˚C 85 ˚C 5 125 ˚C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATtiny25/45/85 Figure 23-23. I/O Pin Sink Current vs. Output Voltage (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT Vc c = 3V 3.5 3 V OH (V 2.5 -40 25 85 125 2 1.5 1 0.5 0 0 5 10 15 20 25 IOH (mA) Figure 23-24. I/O Pin Sink Current vs. Output Voltage (VCC = 5.0V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT Vc c = 5.0V 5.1 5 4.9 V OH (V) 4.8 4.7 4.6 -40 4.5 25 85 125 4.4 4.
23.6 Pin Thresholds and Hysteresis Figure 23-25. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read As '1') I/O P IN INP UT THRES HOLD VOLTAGE vs . V CC VIH, IO PIN READ AS '1' -40 25 85 125 3 2.5 ˚C ˚C ˚C ˚C Thre s hold 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-26. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0') I/O P IN INP UT THRES HOLD VOLTAGE vs . VC C VIL, IO PIN READ AS '0' 125 85 25 -40 2.5 ˚C ˚C ˚C ˚C Thre s hold 2 1.5 1 0.
ATtiny25/45/85 Figure 23-27. I/O Pin Input Hysteresis vs. VCC I/O P IN INP UT HYS TERES IS 0.8 0.7 Thre s hold 0.6 0.5 0.4 -40 25 85 125 0.3 0.2 ˚C ˚C ˚C ˚C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-28. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1') RES ET INP UT THRES HOLD VOLTAGE vs . V C C VIH, IO PIN READ AS '1' 125 85 25 -40 2.5 ˚C ˚C ˚C ˚C Thre s hold 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 23-29. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read As '0') RES ET INP UT THRES HOLD VOLTAGE vs . CVC VIL, IO PIN READ AS '0' 125 85 25 -40 ˚C ˚C ˚C ˚C 125 85 25 5.5 -40 ˚C ˚C ˚C ˚C 2.5 Thre s hold 2 1.5 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-30. Reset Input Pin Hysteresis vs. VCC RES ET INP UT THRES HOLD VOLTAGE vs . CC V VIH, IO PIN READ AS '1' 0.25 Thre s hold 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.
ATtiny25/45/85 23.7 BOD Thresholds and Analog Comparator Offset Figure 23-31. BOD Thresholds vs. Temperature (BODLEVEL Is 4.3V) BOD THRES HOLDS vs . TEMP ERATURE BODLEVEL = 4.3V 4.4 4.35 Ris ing Thre s hold (V) 4.3 Falling 4.25 4.2 4.15 4.1 4.05 4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature (C) Figure 23-32. BOD Thresholds vs. Temperature (BODLEVEL Is 2.7V) BOD THRES HOLDS vs . TEMP ERATURE BODLEVEL = 2.7V 2.8 Ris ing Thre s hold (V) 2.75 2.
Figure 23-33. BOD Thresholds vs. Temperature (BODLEVEL Is 1.8V) BOD THRES HOLDS vs . TEMP ERATURE BODLEVEL at 1.8V 1.9 1.85 Thre s hold (V) Ris ing Vcc 1.8 Falling Vcc 1.75 1.7 1.65 1.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature (C) 23.8 Internal Oscillator Speed Figure 23-34. Watchdog Oscillator Frequency vs. VCC) WATCHDOC OS CILLATOR FREQUENCY vs . V CC 0.118 0.116 -40 ˚C 0.114 25 ˚C FRC (MHz ) 0.112 0.11 0.108 85 ˚C 0.106 0.
ATtiny25/45/85 Figure 23-35. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OS CILLATOR FREQUENCY vs . TEMP ERATURE 0.118 0.116 0.114 FRC (MHz ) 0.112 0.11 0.108 1.8 V 0.106 2.7 3.6 4.0 5.5 0.104 0.102 0.1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 V V V V 100 110 120 Temperature Figure 23-36. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.4 5.0 V 3.0 V 8.3 8.2 FRC (MHz ) 8.1 8 7.9 7.8 7.7 7.6 7.
Figure 23-37. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 8.4 125 ˚C 8.3 85 ˚C 8.2 FRC (MHz ) 8.1 25 ˚C 8 7.9 7.8 -40 ˚C 7.7 7.6 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-38. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs .
ATtiny25/45/85 23.9 Current Consumption of Peripheral Units Figure 23-39. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs . CVC 35 125 85 25 -40 30 ICC (uA) 25 ˚C ˚C ˚C ˚C 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-40. Analog Comparator Current vs. VCC ANALOG COMP ARATOR CURRENT vs . V CC AREF = AVcc 350 150 ˚C 300 125 ˚C 85 ˚C ICC (uA) 250 200 25 ˚C 150 100 50 -40 ˚C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
23.10 Current Consumption in Reset and Reset Pulse width Figure 23-41. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up) RES ET S UP P LY CURRENT vs . CVC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.14 5.5 V 0.12 5.0 V ICC (mA) 0.1 4.5 V 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 23-42. Reset Supply Current vs.
ATtiny25/45/85 Figure 23-43. Reset Pulse Width vs. VCC MINIMUM RES ET P ULS E WIDTH vs . VC C 2500 Puls e width (ns ) 2000 1500 1000 125 85 25 -40 500 ˚C ˚C ˚C ˚C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 23.11 Analog to Digital Converter Figure 23-44. Analog to Digital Converter Differential mode OFFSET vs. VCC Analog to Digital Converter - OFFS ET Diffe re ntia l Inputs , Vc c = 4V, Vre f = 4V 2 1.5 1 0.5 Diff x1 0 -0.5 -1 -1.
Figure 23-45. Analog to Digital Converter Single Endded mode OFFSET vs. VCC Analog to Digital Converter - OFFS ET Single Ended, Vcc = 4V, Vref = 4V 2.5 2 LSB 1.5 1 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 23-46. Analog to Digital Converter Differential mode GAIN vs. VCC Analog to Digital Converter - GAIN Differential Inputs , Vcc = 5V, Vref = 4V -1 -1.2 -1.4 -1.6 Diff x20 LSB -1.8 -2 -2.2 -2.4 -2.6 Diff x1 -2.
ATtiny25/45/85 Figure 23-47. Analog to Digital Converter Single Endded mode GAIN vs. VCC Analog to Digital Converter - GAIN Single Ended, Vcc = 4V, Vref = 4V 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -0.5 LSB -1 -1.5 -2 -2.5 Temperature Figure 23-48. Analog to Digital Converter Differential mode DNL vs. VCC Analog to Digital Converter - Differential Non Linearity DNL Differential Inputs , Vcc = 4V, Vref = 4V 1.2 Diff x20 1 LSB 0.8 0.6 0.4 Diff x1 0.
Figure 23-49. Analog to Digital Converter Single Endded mode DNL vs. VCC Analog to Digital Converter - Differential Non Linearity DNL Single Ended, Vcc = 4V, Vref = 4V 0.57 0.56 0.55 0.54 LSB 0.53 0.52 0.51 0.5 0.49 0.48 0.47 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 23-50. Analog to Digital Converter differential mode INL vs. VCC Analog to Digital Converter - Integral Non Linearity INL Differential Inputs , Vcc = 4V, Vref = 4V 1.8 1.6 Diff x20 1.
ATtiny25/45/85 Figure 23-51. Analog to Digital Converter Single Endded mode INL vs. VCC Analog to Digital Converter - Integral Non Linearity INL Single Ended, Vcc = 4V, Vref = 4V 0.72 0.7 LSB 0.68 0.66 0.64 0.62 0.6 0.
24.
ATtiny25/45/85 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x08 ACSR ACD ACBG ACO ACI ACIE – ACIS1 ACIS0 page 108 0x07 ADMUX REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 page 123 0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 124 0x05 ADCH ADC Data Register High Byte 0x04 ADCL ADC Data Register Low Byte 0x03 ADCSRB 0x02 Reserved – 0x01 Reserved – 0x00 Reserved – Notes: BIN ACME IPR – – page 126 page 126 ADT
25.
ATtiny25/45/85 Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)←Rd(n+1),C←Rd(0) Z,C,N,V ASR Rd Arithmetic Shift Right Rd(n) ←Rd(n+1), n=0..6 Z,C,N,V 1 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
26. Ordering Information Power Supply Notes: Speed (MHz) Ordering Code Package Operation Range 2.7 - 5.5V (3) 8 - 16 ATtiny25/45/85-15ST ATtiny25/45/85-15ST1 ATtiny25/45/85-15SZ T5 Automotive (-40°C to +85°C) Automotive (-40°C to +105°C) Automotive (-40°C to 125°C) 2.7 - 5.5V 8 - 16(3) ATtiny25/45/85-15MT ATtiny25/45/85-15MT1 ATtiny25/45/85-15MZ PC Automotive (-40°C to 85°C) Automotive (-40°C to +105°C) Automotive (-40°C to +125°C) 1. Green and ROHS packaging 2.
ATtiny25/45/85 27. Packaging Information 27.
27.
ATtiny25/45/85 28. Document Revision History 28.1 Revision 7598I - 10/12 1. Section 27 “Package Information” on page 188 updated. 28.2 Revision 7598H - 07/09 1. Absolute Maximum Ratings updated 28.3 Revision 7598G - 03/08 1. Modified See “Power Management and Sleep Modes” on page 31. 2. Modified See “MCU Control Register – MCUCR” on page 31. 3. Modified Active Clock Domains and Wake-up Sources in the Different Sleep Modes33. 4. Added “Limitations” on page 33. 5.
28.9 Changes from Revision 2535A-09/01 to Revision 7598A-04/06 1. Automotive grade created: Features: – Change voltage and temperature range (2.7V - 5.5V), (-40°C, +125°C) – Adapt Stand-by current to automotive temperature range Packages: – PDIP removed – Ordering info limited to Automotive versions (green only, dry pack) DC & AC parameters – Only PRELIMINARY values are produced. 29. Errata The revision letter in this section refers to the revision of the ATtiny25/45/85 device. 29.
ATtiny25/45/85 30. Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 2 2.1 Block Diagram ...................................................................................................3 2.
7 8 9 Power Management and Sleep Modes ................................................. 31 7.1 MCU Control Register – MCUCR ....................................................................31 7.2 Idle Mode .........................................................................................................32 7.3 ADC Noise Reduction Mode ............................................................................32 7.4 Power-down Mode ........................................................
ATtiny25/45/85 12.3 Counter Unit ....................................................................................................62 12.4 Output Compare Unit .......................................................................................63 12.5 Compare Match Output Unit ............................................................................65 12.6 Modes of Operation .........................................................................................66 12.
19.2 Overview ........................................................................................................128 19.3 Physical Interface ..........................................................................................128 19.4 Software Break Points ...................................................................................129 19.5 Limitations of debugWIRE .............................................................................129 19.
ATtiny25/45/85 23.9 Current Consumption of Peripheral Units ......................................................175 23.10 Current Consumption in Reset and Reset Pulse width .................................176 23.11 Analog to Digital Converter ............................................................................177 24 Register Summary .............................................................................. 182 25 Instruction Set Summary ..................................................
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