Datasheet

8183F–AVR–06/12

ATtiny24A/44A/84A

11.9 Register Description

11.9.1 TCCR0A – Timer/Counter Control Register A

• Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A[1:0]

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the

WGM0[2:0] bit setting. Table 11-2 shows the COM0A[1:0] bit functionality when the WGM0[2:0]

bits are set to a normal or CTC mode (non-PWM).

Table 11-3 shows COM0A[1:0] bit functionality when WGM0[1:0] bits are set to fast PWM mode.

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on

page 74 for more details.

Bit 7 6 5 4 3 2 1 0

0x30 (0x50)

COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 11-2. Compare Output Mode, non-PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1 Toggle OC0A on Compare Match

1 0 Clear OC0A on Compare Match

1 1 Set OC0A on Compare Match

Table 11-3. Compare Output Mode, Fast PWM Mode

(1)

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected

WGM02 = 0: Normal Port Operation, OC0A Disconnected

WGM02 = 1: Toggle OC0A on Compare Match

Clear OC0A on Compare Match

Set OC0A at BOTTOM (non-inverting mode)

Set OC0A on Compare Match

Clear OC0A at BOTTOM (inverting mode)