Datasheet

42
8183F–AVR–06/12
ATtiny24A/44A/84A
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can
be very helpful when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 8-1 See “Timed
Sequences for Changing the Configuration of the Watchdog Timer” on page 42 for details.
Figure 8-7. Watchdog Timer
8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
• Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the
WDE bit to one without any restriction. A timed sequence is needed when disabling an
enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure
must be followed:
a. In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE regardless of the previous value of the WDE bit
b. Within the next four clock cycles, in the same operation, write the WDE and WDP
bits as desired, but with the WDCE bit cleared
Table 8-1. WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
Safety
Level
WDT Initial
State
How to Disable the
WDT
How to Change Time-
out
Unprogrammed 1 Disabled Timed sequence No limitations
Programmed 2 Enabled Always enabled Timed sequence
OSC/2K OSC/4K OSC/8K
OSC/16K OSC/32K OSC/64K
OSC/128K OSC/256K
OSC/512K
OSC/1024K
MCU RESET
WATCHDOG
PRESCALER
128 kHz
OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
MUX