Datasheet

149
8183F–AVR–06/12
ATtiny24A/44A/84A
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
See “ADCSRB – ADC Control and Status Register B” on page 130.
• Bit 5 – Res: Reserved Bit
This is a reserved bit in ATtiny24A/44A/84A. For compatibility with future devices always write
this bit to zero.
• Bit 4 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a comple the description of this bit, see “ADCL and ADCH – ADC Data Register” on
page 148.
• Bit 3 – Res: Reserved Bit
This bit is reserved bit in the ATtiny24A/44A/84A and will always read as what was wrote there.
• Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
.
16.13.5 DIDR0 – Digital Input Disable Register 0
• Bits 7:0 – ADC7D:ADC0D: ADC[7:0] Digital Input Disable
When a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled.
The corresponding PIN register bit will always read as zero when this bit is set. When an analog
signal is applied to the ADC[7:0] pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
Table 16-7. ADC Auto Trigger Source Selections
ADTS2 ADTS1 ADTS0 Trigger Source
0 0 0 Free Running mode
0 0 1 Analog Comparator
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare Match A
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter1 Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event
Bit 76543210
0x01 (0x21) ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0