Datasheet

137
8183F–AVR–06/12
ATtiny24A/44A/84A
this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the
trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 16-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. See Figure 16-7.
Figure 16-7. ADC Timing Diagram, Free Running Conversion
1 2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
11 12 13
Si g n an d MSB o f Resu l t
LSB of Result
A
DC Clock
A
DSC
A
DIF
A
DCH
A
DCL
C
ycle Number
12
One Conversion Next Conversion
34
Co n v er si o n
Co m p l et e
Sam p l e & Ho
ld
MUX and REFS
Update