Datasheet

133
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 16-1. Analog to Digital Converter Block Schematic
16.3 Operation
In order to be able to use the ADC the Power Reduction bit, PRADC, in the Power Reduction
Register must be disabled. This is done by clearing the PRADC bit. See “PRR – Power Reduc-
tion Register” on page 37 for more details.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and
input channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared, so it is recommended to switch off the ADC before entering power
saving sleep modes.
The ADC converts an analog input voltage to a 10-bit digital value using successive approxima-
tion. The minimum value represents GND and the maximum value represents the reference
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
15 0
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL. & STATUS A
REGISTER (ADCSRA)
ADC DATA REGISTER
(ADCH/ADCL)
ADIE
ADATE
ADSC
ADEN
ADIF
ADIF
MUX[4:0]
ADPS0
ADPS1
ADPS2
CONVERSION LOGIC
10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
INTERNAL
REFERENCE
1.1V
MUX DECODER
V
CC
ADC7
ADC6
ADC5
ADC4
REFS[1:0]
ADLAR
CHANNEL SELECTION
ADC[9:0]
ADC MULTIPLEXER
OUTPUT
PRESCALER
TRIGGER
SELECT
ADTS[2:0]
INTERRUPT
FLAGS
START
+
-
GAIN SELECTION
GAIN
AMPLIFIER
NEG.
INPUT
MUX
SINGLE ENDED / DIFFERENTIAL SELECTION
TEMPERATURE
SENSOR
ADC8
BIN
ADC3
ADC2
ADC1
ADC0
POS.
INPUT
MUX
AGND
ADC CTRL. & STATUS B
REGISTER (ADCSRB)
AREF