Datasheet

129
8183F–AVR–06/12
ATtiny24A/44A/84A
15-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the analog
comparator.
15.2 Register Description
15.2.1 ACSR – Analog Comparator Control and Status Register
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed, internal bandgap reference voltage replaces the positive input to the
Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog
Comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
Table 15-1. Analog Comparator Multiplexed Input
ACME ADEN MUX[4:0] Analog Comparator Negative Input
0 X XXXXX AIN1
1 1 XXXXX AIN1
1 0 00000 ADC0
1 0 00001 ADC1
1 0 00010 ADC2
1 0 00011 ADC3
1 0 00100 ADC4
1 0 00101 ADC5
1 0 00110 ADC6
1 0 00111 ADC7
Bit 76543210
0x08 (0x28) ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 N/A 0 0 0 0 0