Datasheet

114
8183F–AVR–06/12
ATtiny24A/44A/84A
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
ExtClk
< f
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0
Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 13-1 on page 113.
13.3 Register Description
13.3.1 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
PSR10
Clear
clk
T0
T0
clk
I/O
Synchronization
Bit 7 6 5 4 3 2 1 0
0x23 (0x43) TSM
– – – – – – PSR10 GTCCR
Read/Write R/W R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0