Features • High Performance, Low Power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation High Endurance, Non-volatile Memory Segments – 2K/4K/8K Bytes of In-System, Self-programmable Flash Program Memory • Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256/512 B
1. Pin Configurations Figure 1-1. Pinout of ATtiny24A/44A/84A PDIP/SOIC VCC (PCINT8/XTAL1/CLKI) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND PA0 (ADC0/AREF/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/T0/PCINT3) PA4 (ADC4/USCK/SCL/T1/PCINT4) PA5 (ADC5/DO/MISO/OC1B/PCINT5) NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect Table 1-1.
ATtiny24A/44A/84A 1.1 1.1.1 Pin Descriptions VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3:PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse.
2. Overview ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1.
ATtiny24A/44A/84A The ATtiny24A/44A/84A provides the following features: 2K/4K/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal oscilla
3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
ATtiny24A/44A/84A 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATtiny24A/44A/84A The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from an interrupt. This must be handled by software. 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
X-register 7 0 R27 (0x1B) 15 Y-register YH 7 YL 0 0 7 0 R28 (0x1C) 15 ZH 7 0 R31 (0x1F) 0 R26 (0x1A) R29 (0x1D) Z-register 7 ZL 7 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.
ATtiny24A/44A/84A Figure 4-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5.
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.
ATtiny24A/44A/84A When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example.
4.8.2 SREG – AVR Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
ATtiny24A/44A/84A 5. Memories This section describes the different memories in the ATtiny24A/44A/84A. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny24A/44A/84A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 5.1 In-System Re-programmable Flash Program Memory The ATtiny24A/44A/84A contains 2K/4K/8K byte On-chip In-System Reprogrammable Flash memory for program storage.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny24A/44A/84A are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 9. Figure 5-2.
ATtiny24A/44A/84A 5.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 22. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down.
The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on page 31. 5.3.6 Program Examples The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny24A/44A/84A The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 5.4 I/O Memory The I/O space definition of the ATtiny24A/44A/84A is shown in “Register Summary” on page 266. All ATtiny24A/44A/84A I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
ATtiny24A/44A/84A 5.5.2 EEARL – EEPROM Address Register Bit 7 6 5 4 3 2 1 0 0x1E (0x3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X EEARL • Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny44A. In devices with less EEPROM, i.e. ATtiny24A, this bit is reserved and will always read zero.
old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. Table 5-1. EEPROM Programming Mode Bits and Programming Times EEPM1 EEPM0 Programming Time Operation 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use When EEPE is set any write to EEPMn will be ignored.
ATtiny24A/44A/84A 5.5.6 GPIOR1 – General Purpose I/O Register 1 Bit 5.5.
6. Clock System Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 33. Figure 6-1.
ATtiny24A/44A/84A 6.1.2 I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. 6.1.3 Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 6.1.
6.2.1 External Clock To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-2 on page 26. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 6-2. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL CLKI GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-3. Table 6-3.
ATtiny24A/44A/84A By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on page 31, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 20-2 on page 175. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out.
6.2.4 Low-Frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be selected by setting CKSEL fuses to ‘0110’. The crystal should be connected as shown in Figure 6-3. To find suitable capacitors please consult the manufacturer’s datasheet. For this oscillator start-up times can be set with the SUT fuses, as shown in Table 6-7. Table 6-7.
ATtiny24A/44A/84A use with crystals are given in Table 6-9 below. For ceramic resonators, the capacitor values given by the manufacturer should be used. Table 6-9. Crystal Oscillator Operating Modes CKSEL[3:1] Frequency Range (MHz) Recommended C1 and C2 Value (pF) 100(1) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 Notes: 1. This option should not be used with crystals, only with ceramic resonators.
6.2.6 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal Oscillator running at 8.0 MHz with longest start-up time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This default setting ensures that all users can make their desired clock source setting using an in-system or high-voltage programmer. At low voltages (below 2.
ATtiny24A/44A/84A 6.5 6.5.1 Register Description OSCCAL – Oscillator Calibration Register Bit 7 6 5 4 3 2 1 0 0x31 (0x51) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 6-11 on page 32.
ATtiny24A/44A/84A 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
the Analog Comparator can be powered down by setting the ACD bit in “ACSR – Analog Comparator Control and Status Register” on page 129. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.
ATtiny24A/44A/84A 7.3 Power Reduction Register The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 37, provides a method to reduce power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is stopped then: • The current state of the peripheral is frozen. • The associated registers can not be read or written. • Resources used by the peripheral will remain occupied.
turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. See “Internal Voltage Reference” on page 41 for details on the start-up time. 7.4.5 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power.
ATtiny24A/44A/84A • Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1 and 0 These bits select between available sleep modes, as shown in Table 7-2. Table 7-2. Note: Sleep Mode Select SM1 SM0 Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Standby(1) 1. Only recommended with external crystal or resonator selected as clock source • Bit 2 – BODSE: BOD Sleep Enable The BODSE bit enables setting of BODS control bit, as explained on BODS bit description.
8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic.
ATtiny24A/44A/84A 8.2 Reset Sources The ATtiny24A/44A/84A has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT) • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled • Brown-out Reset.
8.2.2 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 176) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired. Figure 8-4.
ATtiny24A/44A/84A 8.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. See “Watchdog Timer” on page 41 for details on operation of the Watchdog Timer. Figure 8-6. Watchdog Reset During Operation CC CK 8.3 Internal Voltage Reference ATtiny24A/44A/84A features an internal bandgap reference.
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-1 See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 42 for details. Table 8-1.
ATtiny24A/44A/84A • Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: a. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence b.
8.5 8.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero.
ATtiny24A/44A/84A the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-2. Watchdog Timer Configuration WDE WDIE Watchdog Timer State Action on Time-out 0 0 Stopped None 0 1 Running Interrupt 1 0 Running Reset 1 1 Running Interrupt • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled.
• Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1, and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 8-3. Table 8-3. WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K cycles 16 ms 0 0 0 1 4K cycles 32 ms 0 0 1 0 8K cycles 64 ms 0 0 1 1 16K cycles 0.125 s 0 1 0 0 32K cycles 0.
ATtiny24A/44A/84A 9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny24A/44A/84A. For a general explanation of the AVR interrupt handling, see “Reset and Interrupt Handling” on page 11. 9.1 Interrupt Vectors The interrupt vectors of ATtiny24A/44A/84A are described in Table 9-1 below. Table 9-1. Reset and Interrupt Vectors Vector No.
Address Labels Code Comments 0x0000 rjmp RESET ; Reset Handler 0x0001 rjmp INT0 ; IRQ0 Handler 0x0002 rjmp PCINT0 ; PCINT0 Handler 0x0003 rjmp PCINT1 ; PCINT1 Handler 0x0004 rjmp WDT ; Watchdog Interrupt Handler 0x0005 rjmp TIM1_CAPT ; Timer1 Capture Handler 0x0006 rjmp TIM1_COMPA ; Timer1 Compare A Handler 0x0007 rjmp TIM1_COMPB ; Timer1 Compare B Handler 0x0008 rjmp TIM1_OVF ; Timer1 Overflow Handler 0x0009 rjmp TIM0_COMPA ; Timer0 Compare A Handler 0x000A rjmp
ATtiny24A/44A/84A Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses, as described in “Clock System” on page 24.
9.3 9.3.1 Register Description MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.
ATtiny24A/44A/84A • Bit 4 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register. 9.3.
9.3.5 PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 0x12 (0x32) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 • Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0 Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
ATtiny24A/44A/84A 10. I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
10.1 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 10.1.
ATtiny24A/44A/84A 10.1.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.1.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
ATtiny24A/44A/84A important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 10.1.7 Program Examples The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4.
10.2 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. In Figure 10-5 below is shown how the port pin control signals from the simplified Figure 10-2 on page 54 can be overridden by alternate functions. Figure 10-5.
ATtiny24A/44A/84A Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
10.2.1 Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. Table 10-3.
ATtiny24A/44A/84A • Port A, Bit 1 – ADC1/AIN0/PCINT1 • ADC1: Analog to Digital Converter, Channel 1. • AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pullup switched off to avoid the digital port function from interfering with the function of the Analog Comparator. • PCINT1: Pin Change Interrupt source 1. The PA1 pin can serve as an external interrupt source for pin change interrupt 0.
• Port A, Bit 6 – ADC6/DI/SDA/MOSI/OC1A/PCINT6 • ADC6: Analog to Digital Converter, Channel 6. • SDA: Two-wire mode Serial Interface Data. • DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. • MOSI: Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDA6.
ATtiny24A/44A/84A Table 10-5.
10.2.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-7. Table 10-7.
ATtiny24A/44A/84A • Port B, Bit 3 – RESET/dW/PCINT11 • RESET: External Reset input is active low and enabled by unprogramming (“1”) the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. • dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated.
Table 10-9. Signal Name Overriding Signals for Alternate Functions in PB[1:0] PB1/XTAL2/PCINT9 PB0/XTAL1/PCINT8 (1) EXT_CLOCK (2) + EXT_OSC(1) PUOE EXT_OSC PUOV 0 0 DDOE EXT_OSC(1) EXT_CLOCK(2) + EXT_OSC(1) DDOV 0 0 (1) PVOE EXT_OSC EXT_CLOCK(2) + EXT_OSC(1) PVOV 0 0 PTOE 0 0 (1) 10.3 10.3.
ATtiny24A/44A/84A 10.3.4 PINA – Port A Input Pins Bit 10.3.5 10.3.6 10.3.
11. 8-bit Timer/Counter0 with PWM 11.1 Features • • • • • • • 11.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
ATtiny24A/44A/84A 11.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in Figure 11-1) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin.
Figure 11-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count direction clear clkTn top bottom Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clkT0 in the following. Signalize that TCNT0 has reached maximum value.
ATtiny24A/44A/84A Figure 11-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) m Waveform Generator OCnx n The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x[1:0] bits are not double buffered together with the compare value. Changing the COM0x[1:0] bits will take effect immediately. 11.
ATtiny24A/44A/84A 11.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x[1:0] = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 11-2 on page 79. For fast PWM mode, refer to Table 11-3 on page 79, and for phase correct PWM refer to Table 11-4 on page 80.
Figure 11-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATtiny24A/44A/84A PWM mode is shown in Figure 11-6 on page 75. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 11-6.
similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 11.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM0[2:0] = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 1, and OCR0A when WGM0[2:0] = 5.
ATtiny24A/44A/84A PWM output can be generated by setting the COM0x[1:0] to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 11-4 on page 80). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) MAX - 1 TCNTn MAX BOTTOM BOTTOM + 1 TOVn Figure 11-10 on page 78 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 11-10.
ATtiny24A/44A/84A 11.9 11.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x30 (0x50) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
Table 11-4 shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Table 11-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting.
ATtiny24A/44A/84A Table 11-7 shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Table 11-7. Compare Output Mode, Phase Correct PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
11.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x33 (0x53) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
ATtiny24A/44A/84A Table 11-9. Clock Select Bit Description (Continued) CS02 CS01 CS00 Description 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output.
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.
ATtiny24A/44A/84A 12. 16-bit Timer/Counter1 12.1 Features • • • • • • • • • • • 12.2 True 16-bit Design (i.e.
Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. 12.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers.
ATtiny24A/44A/84A 12.2.3 Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. • Interrupt Vectors.
Description of internal signals used in Figure 12-2: Count Direction Clear clkT1 TOP BOTTOM Increment or decrement TCNT1 by 1. Select between increment and decrement. Clear TCNT1 (set all bits to zero). Timer/Counter clock. Signalize that TCNT1 has reached maximum value. Signalize that TCNT1 has reached minimum value (zero).
ATtiny24A/44A/84A Figure 12-3. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO* Analog Comparator ACIC* TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.
(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 13-1 on page 113). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles.
ATtiny24A/44A/84A are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 94). A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 12-4 on page 91 shows a block diagram of the Output Compare unit.
updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 103. 12.6.
ATtiny24A/44A/84A Figure 12-5. Compare Match Output Unit, Schematic (non-PWM Mode) COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x[1:0] bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
12.8 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM1[3:0]) and Compare Output mode (COM1x[1:0]) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATtiny24A/44A/84A Figure 12-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA[1:0] = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
ATtiny24A/44A/84A ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
ATtiny24A/44A/84A result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length.
the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM1[3:0] = 8), or the value in OCR1A (WGM1[3:0] = 9). The counter has then reached the TOP and changes the count direction.
ATtiny24A/44A/84A Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 12-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATtiny24A/44A/84A Figure 12-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value 12.10 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus.
Assembly Code Examples ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: See “Code Examples” on page 6. The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
ATtiny24A/44A/84A C Code Example unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: See “Code Examples” on page 6. The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how to do an atomic write of the TCNT1 Register contents.
C Code Example void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; } Note: See “Code Examples” on page 6. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 12.10.
ATtiny24A/44A/84A Table 12-2 shows COM1x[1:0] bit functionality when WGM1[3:0] bits are set to a Normal or a CTC mode (non-PWM). Table 12-2. Compare Output Mode, non-PWM COM1A1 COM1B1 COM1A0 COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected 0 1 Toggle OC1A/OC1B on Compare Match 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level) 1 1 Set OC1A/OC1B on Compare Match (Set output to high level).
• Bits 1:0 – WGM1[1:0]: Waveform Generation Mode Combined with the WGM1[3:2] bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 12-5 on page 108. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (“Modes of Operation” on page 94).
ATtiny24A/44A/84A When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM1[3:0] bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x[1:0] bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bits 5:0 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. 12.11.
ATtiny24A/44A/84A 12.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 0x25 (0x45) ICR1[15:8] 0x24 (0x44) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
12.11.9 TIFR1 – Timer/Counter Interrupt Flag Register 1 Bit 7 6 5 4 3 2 1 0 0x0B (0x2B) – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin.
ATtiny24A/44A/84A 13. Timer/Counter Prescaler Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counters. Tn is used as a general name, n = 0, 1. The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle.
ATtiny24A/44A/84A ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting. • Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n When this bit is one, the Timer/Countern prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.
14. USI – Universal Serial Interface 14.1 Features • • • • • • 14.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication.
ATtiny24A/44A/84A The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges.
Figure 14-3. CYCLE Three-wire Mode, Timing Diagram ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The three-wire mode timing is shown in Figure 14-3 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
ATtiny24A/44A/84A SPITransfer_loop: out USICR,r17 in r16, USISR sbrs r16, USIOIF rjmp SPITransfer_loop in r16,USIDR ret The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16.
14.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
ATtiny24A/44A/84A Figure 14-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER The data direction is not given by the physical layer. A protocol, like the one used by the TWIbus, must be implemented to control the data flow. Figure 14-5.
4. After eight bits containing slave address and data direction (read or write) have been transferred, the slave counter overflows and the SCL line is forced low (D). If the slave is not the one the master has addressed, it releases the SCL line and waits for a new start condition. 5. When the slave is addressed, it holds the SDA line low during the acknowledgment cycle before holding the SCL line low again (i.e., the USI Counter Register must be set to 14 before releasing SCL at (D)).
ATtiny24A/44A/84A 14.4 Alternative USI Usage The flexible design of the USI allows it to be used for other tasks when serial communication is not needed. Below are some examples. 14.4.1 Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire mode it is possible to implement a more compact and higher performance UART than by software, only. 14.4.2 4-Bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt.
Data Register can therefore be clocked externally and data input sampled, even when outputs are disabled. Table 14-1. Relationship between USIWM[1:0] and USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operate as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORTA register. However, the corresponding DDRA bit still controls the data direction.
ATtiny24A/44A/84A Table 14-2 shows the relationship between the USICS[1:0] and USICLK setting and clock source used for the USI Data Register and the 4-bit counter. Table 14-2.
If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be generated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of USCL in two-wire mode. A start condition interrupt will wakeup the processor from all sleep modes. • Bit 6 – USIOIF: Counter Overflow Interrupt Flag This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0).
ATtiny24A/44A/84A Note that even when no wire mode is selected (USIWM[1:0] = 0) both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register. The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input is sampled and data output is changed on opposite clock edges.
15. Analog Comparator The analog comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 15-1.
ATtiny24A/44A/84A 15-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the analog comparator. Table 15-1. 15.2 15.2.
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
ATtiny24A/44A/84A 15.2.3 DIDR0 – Digital Input Disable Register 0 Bit 7 6 5 4 3 2 1 0 0x01 (0x21) ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR0 • Bits 2:1 – ADC2D, ADC1D: ADC[2:1] Digital input buffer disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
16. Analog to Digital Converter 16.1 Features • • • • • • • • • • • • • • • • • 16.2 10-bit Resolution 1 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 13 µs Conversion Time 15 kSPS at Maximum Resolution Eight Multiplexed Single Ended Input Channels Twelve Differential Input Channels with Selectable Gain (1x, 20x) Temperature Sensor Input Channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 1.
ATtiny24A/44A/84A Figure 16-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] AREF 0 ADC DATA REGISTER (ADCH/ADCL) ADC[9:0] ADPS0 ADPS1 ADPS2 ADSC ADIF ADEN ADLAR MUX[4:0] REFS[1:0] BIN 15 ADC CTRL. & STATUS A REGISTER (ADCSRA) ADC MULTIPLEXER SELECT (ADMUX) ADATE ADC CTRL. & STATUS B REGISTER (ADCSRB) ADIE ADIF 8-BIT DATA BUS TRIGGER SELECT MUX DECODER PRESCALER INTERNAL REFERENCE 1.
voltage. The ADC voltage reference is selected by writing the REFS[1:0] bits in the ADMUX register. Alternatives are the VCC supply pin, the AREF pin and the internal 1.1V voltage reference. The analog input channel and differential gain are selected by writing to the MUX bits in ADMUX. Any of the ADC input pins can be selected as single ended inputs to the ADC. For differential measurements all analog inputs next to each other can be selected as input pairs.
ATtiny24A/44A/84A be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. Figure 16-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished.
The ADC module contains a prescaler, as illustrated in Figure 16-3 on page 135, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
ATtiny24A/44A/84A this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. Figure 16-6.
For a summary of conversion times, see Table 16-1. Table 16-1. ADC Conversion Time Condition Sample & Hold (Cycles from Start of Conversion) First conversion 13.5 25 Normal conversions 1.5 13 2 13.5 2.5 13 Auto Triggered conversions Free Running conversion 16.6 Conversion Time (Cycles) Changing Channel or Reference Selection The MUX[5:0] and REFS[1:0] bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access.
ATtiny24A/44A/84A channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 16.6.2 ADC Voltage Reference The ADC reference voltage (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V reference, or external AREF pin. The internal 1.
In order to avoid distortion from unpredictable signal convolution, signal components higher than the Nyquist frequency (fADC/2) should not be present. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 16-8. Analog Input Circuitry IIH ADCn 1..100 kohm CS/H = 14 pF IIL VCC/2 Note: 16.
ATtiny24A/44A/84A • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 16-9. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 16-10.
Figure 16-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
ATtiny24A/44A/84A 16.11.3 Bipolar Differential Conversion If differential channels and a bipolar input mode are used, the result is ( V POS – V NEG ) ⋅ 512 ADC = ----------------------------------------------------- ⋅ GAIN V REF where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference. The result is presented in two’s complement form, from 0x200 (-512d) through 0x1FF (+511d). The GAIN is either 1x or 20x.
16.13 Register Description 16.13.1 ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 0x07 (0x27) REFS1 REFS0 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bits 7:6 – REFS[1:0]: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 16-3. Table 16-3.
ATtiny24A/44A/84A done by first turning off the ADC, then changing multiplexer settings and then turn on the ADC. Alternatively, the first conversion results after changing multiplexer settings should be discarded. Table 16-4.
Table 16-5. Differential Input channel Selections.
ATtiny24A/44A/84A • Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC.
16.13.3 16.13.3.1 ADCL and ADCH – ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 0x05 (0x25) – – – – – – ADC9 ADC8 ADCH 0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 16.13.3.
ATtiny24A/44A/84A • Bit 6 – ACME: Analog Comparator Multiplexer Enable See “ADCSRB – ADC Control and Status Register B” on page 130. • Bit 5 – Res: Reserved Bit This is a reserved bit in ATtiny24A/44A/84A. For compatibility with future devices always write this bit to zero. • Bit 4 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.
17. debugWIRE On-chip Debug System 17.1 Features • • • • • • • • • • 17.
ATtiny24A/44A/84A When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 17.
18. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”). The Program memory is updated in a page by page fashion.
ATtiny24A/44A/84A If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 18.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. Note: 18.
18.5 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 18.6 Reading Lock, Fuse and Signature Data from Software It is possible for firmware to read device fuse and lock bits.
ATtiny24A/44A/84A To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 Refer to Table 19-4 on page 159 for detailed description and mapping of the Fuse High Byte. To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous procedure.
18.7 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
ATtiny24A/44A/84A imprint table into the destination register. See “Device Signature Imprint Table” on page 160 for details. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.
19. Memory Programming This section describes the different methods for programming ATtiny24A/44A/84A memories. 19.1 Program And Data Memory Lock Bits The ATtiny24A/44A/84A provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 19-2. The lock bits can only be erased to “1” with the Chip Erase command. The device has no separate boot loader section.
ATtiny24A/44A/84A 19.2 Fuse Bytes The ATtiny24A/44A/84A have three fuse bytes. Table 19-3, Table 19-4 and Table 19-5 briefly describe the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 19-3.
Table 19-5. Fuse Low Byte Fuse Low Byte (1) CKOUT (2) CKDIV8 SUT1 (3) SUT0 (3) Bit No Description Default Value 7 Divide clock by 8 0 (programmed) 6 Clock Output Enable 1 (unprogrammed) 5 Select start-up time 1 (unprogrammed) 4 Select start-up time 0 (programmed) (4) 3 Select Clock source 0 (programmed) CKSEL2 (4) 2 Select Clock source 0 (programmed) CKSEL1 (4) 1 Select Clock source 1 (unprogrammed) (4) 0 Select Clock source 0 (programmed) CKSEL3 CKSEL0 Notes: 1.
ATtiny24A/44A/84A 19.3.1 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and High-voltage Programming mode, also when the device is locked. Signature bytes can also be read by the device firmware. See section “Reading Lock, Fuse and Signature Data from Software” on page 154. The three signature bytes reside in a separate address space called the device signature imprint table.
19.5 Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See Figure 19-1 below. Figure 19-1. Serial Programming and Verify +1.8 - 5.5V VCC MOSI MISO SCK RESET GND Note: If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.
ATtiny24A/44A/84A Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: • Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz • High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 19.5.1 Serial Programming Algorithm When writing serial data to the ATtiny24A/44A/84A, data is clocked on the rising edge of SCK.
7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 19-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location 19.5.2 Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 9.0 ms tWD_FUSE 4.5 ms Serial Programming Instruction set The instruction set is described in Table 19-12 and Figure 19-2 on page 165. Table 19-12.
ATtiny24A/44A/84A Table 19-12. Serial Programming Instruction Set (Continued) Instruction Format (1) Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4 Write Lock bits $AC $E0 $00 data byte in Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte in Notes: 1. Not all instructions are applicable for all parts. 2. a = address 3. Bits are programmed ‘0’, unprogrammed ‘1’. 4.
After data is loaded to the page buffer, program the EEPROM page, see Figure 19-2 on page 165. 19.6 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATtiny24A/44A/84A. Figure 19-3. High-voltage Serial Programming +11.5 - 12.5V SCI +4.5 - 5.5V PB3 (RESET) VCC PB0 PA4 SDO PA2:0 PA5 SII GND PA6 SDI Table 19-13.
ATtiny24A/44A/84A 19.7.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Set Prog_enable pins listed in Table 19-14 on page 166 to “000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. Ensure that VCC reaches at least 1.8V within the next 20 µs. 3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET. 4.
19.7.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. • The command needs only be loaded once when writing or reading multiple memory locations. • Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase.
ATtiny24A/44A/84A Figure 19-4. Addressing the Flash which is Organized in Pages PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Figure 19-5. High-voltage Serial Programming Waveforms SDI PA6 MSB LSB SII PA5 MSB LSB SDO PA4 SCI PB0 19.7.
19.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to Table 19-16 on page 170): 1. Load Command "Read Flash". 2. Read Flash Low and High Bytes. The contents at the selected address are available at serial output SDO. 19.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Table 19-16 on page 170): 1. Load Command “Read EEPROM”. 2. Read EEPROM Byte. The contents at the selected address are available at serial output SDO. 19.7.
ATtiny24A/44A/84A Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24A/44A/84A (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3/7 Instr.
Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24A/44A/84A (Continued) Instruction Format Instruction Write Lock Bits Read Fuse Low Bits Read Fuse High Bits Instr.1/5 Instr.2/6 Instr.3/7 Instr.
ATtiny24A/44A/84A 20. Electrical Characteristics 20.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Table 20-1. Symbol DC Characteristics. TA = -40°C to +85°C (Continued) Parameter Supply Current, Active Mode (9) ICC Supply Current, Idle Mode (9) Supply Current, Power-Down Mode (10) Notes: Typ(1) Max Units f = 1 MHz, VCC = 2V 0.25 0.5 mA f = 4 MHz, VCC = 3V 1.2 2 mA f = 8 MHz, VCC = 5V 4.4 7 mA f = 1 MHz, VCC = 2V 0.04 0.2 mA f = 4 MHz, VCC = 3V 0.25 0.6 mA f = 8 MHz, VCC = 5V 1.3 2 mA WDT enabled, VCC = 3V 4 10 µA WDT disabled, VCC = 3V 0.13 2 µA Condition Min 1.
ATtiny24A/44A/84A 20.4 Clock Characteristics 20.4.1 Accuracy of Calibrated Internal Oscillator It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 21-109 on page 237 and Figure 21-110 on page 238. Table 20-2.
20.5 System and Reset Characteristics Table 20-4. Symbol Parameter VRST RESET pin threshold voltage tRST Minimum pulse width on RESET pin Condition Min(1) Typ(1) 0.2 VCC Max(1) Units 0.9VCC V 2000 700 400 ns Brown-out Detector hysteresis 50 mV tBOD Minimum pulse width on Brown-out Reset 2 µs VBG Internal bandgap reference voltage VCC = 5V TA = 25°C tBG Internal bandgap reference start-up time IBG Internal bandgap reference current consumption VHYST Note: 20.5.
ATtiny24A/44A/84A 20.6 ADC Characteristics Table 20-7. Symbol ADC Characteristics, Single Ended Channels. T = -40°C to +85°C Parameter Condition Min Typ Resolution Units 10 Bits VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2.0 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz 2.5 LSB VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
Table 20-8.
ATtiny24A/44A/84A Table 20-9.
20.7 Analog Comparator Characteristics Table 20-10. Analog Comparator Characteristics, TA = -40°C to +85°C Symbol Parameter Condition VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 Digital Propagation Delay VCC = 1.8V - 5.
ATtiny24A/44A/84A Table 20-11. Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted) Symbol tCLCL Min Oscillator Period (VCC = 4.5V - 5.5V) Typ Max 50 SCK Pulse Width High tSHSL Units ns 2 tCLCL (1) ns 2 tCLCL (1) ns tSLSH SCK Pulse Width Low tOVSH MOSI Setup to SCK High tCLCL ns MOSI Hold after SCK High 2 tCLCL ns tSHOX Note: 20.9 Parameter 1.
21. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
ATtiny24A/44A/84A Table 21-2. Additional Current Consumption (percentage) in Active and Idle mode Current consumption additional to active mode with external clock (see Figure 21-56 and Figure 21-57) PRR bit 21.1.1 Current consumption additional to idle mode with external clock (see Figure 21-61 and Figure 21-62) PRTIM1 1% 5% PRTIM0 3% 10 % PRUSI 1% 5% PRADC 5% 20 % Example Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled at VCC = 2.0V and f = 1 MHz.
Figure 21-2. Active Supply Current vs. Frequency 1 - 20 MHz, PRR = 0xFF 12 10 5.5 V 5.0 V 8 ICC (mA) 4.5 V 6 4.0 V 4 3.3 V 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 21-3. Active Supply Current vs.
ATtiny24A/44A/84A Figure 21-4. Active Supply Current vs. VCC Internal RC Oscillator, 1 MHz 1,2 85 °C 25 °C -40 °C 1 ICC (mA) 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-5. Active Supply Current vs.
21.2.2 Current Consumption in Idle Mode Figure 21-6. Idle Supply Current vs. Low Frequency 0.1 - 1.0 MHz, PRR = 0xFF 0,14 5.5 V 0,12 5.0 V 0,1 ICC (mA) 4.5 V 0,08 4.0 V 0,06 3.3 V 2.7 V 0,04 1.8 V 0,02 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 21-7. Idle Supply Current vs. Frequency 1 - 20 MHz, PRR = 0xFF 4 3,5 3 ICC (mA) 2,5 5.5 V 5.0 V 2 4.5 V 1,5 4.0 V 1 3.3 V 0,5 2.7 V 1.
ATtiny24A/44A/84A Figure 21-8. Idle Supply Current vs. VCC Internal RC Oscillator, 8 MHz 2 1,8 1,6 1,4 85 °C 25 °C -40 °C ICC (mA) 1,2 1 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-9. Idle Supply Current vs.
Figure 21-10. Idle Supply Current vs. VCC Internal RC Oscillator, 128 kHz 0,03 0,025 -40 °C 25 °C 85 °C ICC (mA) 0,02 0,015 0,01 0,005 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 21.2.3 Current Consumption in Power-down Mode Figure 21-11. Power-down Supply Current vs.
ATtiny24A/44A/84A Figure 21-12. Power-down Supply Current vs. VCC Watchdog Timer Enabled 10 8 -40 °C 25 °C 85 °C ICC (uA) 6 4 2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 21.2.4 Current Consumption in Reset Figure 21-13. Reset Supply Current vs. VCC 0.1 - 1.0 MHz, Excluding Current through Reset Pull-up 0,16 0,14 0,12 5.5 V 0,1 ICC (mA) 5.0 V 4.5 V 0,08 4.0 V 0,06 3.3 V 2.7 V 0,04 1.
Figure 21-14. Reset Supply Current vs. VCC 1 - 20 MHz, Excluding Current through Reset Pull-up 3 2,5 5.5 V 2 ICC (mA) 5.0 V 4.5 V 1,5 4.0 V 1 3.3 V 2.7 V 0,5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 21.2.5 Current Consumption of Peripheral Units Figure 21-15. ADC Current vs.
ATtiny24A/44A/84A Figure 21-16. AREF Pin Current vs. Pin Voltage 200 180 160 AREF pin current (uA) 140 120 100 80 60 40 20 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 4 4,5 5 5,5 AREF (V) Figure 21-17. Analog Comparator Current vs.
Figure 21-18. Programming Current vs. VCC 10000 9000 -40 °C 8000 7000 ICC (uA) 6000 25 °C 5000 4000 85 °C 3000 2000 1000 0 1,5 2,5 3,5 4,5 5,5 VCC (V) Figure 21-19. Brownout Detector Current vs. VCC BOD Level = 1.
ATtiny24A/44A/84A Figure 21-20. Watchdog Timer Current vs. VCC 8 -40 °C 7 25 °C 85 °C 6 ICC (uA) 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 21.2.6 Pull-up Resistors Figure 21-21. Pull-up Resistor Current vs. Input Voltage I/O Pin, VCC = 1.
Figure 21-22. Pull-up Resistor Current vs. Input Voltage I/O Pin, VCC = 2.7V 80 70 60 IOP (uA) 50 40 30 20 10 25 °C 85 °C -40 °C 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 21-23. Pull-up Resistor Current vs.
ATtiny24A/44A/84A Figure 21-24. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 1.8V 40 35 30 IRESET (uA) 25 25 °C -40 °C 20 85 °C 15 10 5 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET (V) Figure 21-25. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 2.
Figure 21-26. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 5V 120 100 IRESET (uA) 80 25 °C 60 -40 °C 85 °C 40 20 0 0 1 2 3 4 5 6 VRESET (V) 21.2.7 Output Driver Strength Figure 21-27. VOL: Output Voltage vs.
ATtiny24A/44A/84A Figure 21-28. VOL: Output Voltage vs. Sink Current I/O Pin, VCC = 5V 0,6 85 °C 0,5 25 °C VOL (V) 0,4 -40 °C 0,3 0,2 0,1 0 0 5 10 15 20 IOL (mA) Figure 21-29. VOH: Output Voltage vs.
Figure 21-30. VOH: Output Voltage vs. Source Current I/O Pin, VCC = 5V 5,2 5 VOH (V) 4,8 4,6 -40 °C 25 °C 85 °C 4,4 4,2 0 10 5 15 20 IOH (mA) Figure 21-31. VOL: Output Voltage vs.
ATtiny24A/44A/84A Figure 21-32. VOL: Output Voltage vs. Sink Current Reset Pin as I/O, VCC = 5V 1,2 85 °C 1 VOL (V) 0,8 25 °C 0,6 -40 °C 0,4 0,2 0 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 IOL (mA) Figure 21-33. VOH: Output Voltage vs.
Figure 21-34. VOH: Output Voltage vs. Source Current Reset Pin as I/O, VCC = 5V 4,5 4 3,5 VOH (V) 3 -40 °C 25 °C 85 °C 2,5 2 1,5 1 0,5 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 IOH (mA) 21.2.8 Input Threshold and Hysteresis (for I/O Ports) Figure 21-35. VIH: Input Threshold Voltage vs.
ATtiny24A/44A/84A Figure 21-36. VIL: Input Threshold Voltage vs. VCC I/O Pin, Read as ‘0’ 2,5 Threshold (V) 2 1,5 85 °C 25 °C -40 °C 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 4 4,5 5 5,5 VCC (V) Figure 21-37. VIH-VIL: Input Hysteresis vs.
Figure 21-38. VIH: Input Threshold Voltage vs. VCC Reset Pin as I/O, Read as ‘1’ 3 2,5 Threshold (V) 2 1,5 25 °C 85 °C -40 °C 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-39. VIL: Input Threshold Voltage vs.
ATtiny24A/44A/84A Figure 21-40. VIH-VIL: Input Hysteresis vs. VCC Reset Pin as I/O 1 0.9 0.8 -40 °C Input Hysteresis (V) 0.7 25 °C 0.6 0.5 85 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 21.2.9 BOD, Bandgap and Reset Figure 21-41. BOD Threshold vs. Temperature BODLEVEL is 4.
Figure 21-42. BOD Threshold vs. Temperature BODLEVEL is 2.7V 2,8 RISING V CC 2,78 Threshold (V) 2,76 2,74 2,72 FALLING VCC 2,7 2,68 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Figure 21-43. BOD Threshold vs. Temperature BODLEVEL is 1.
ATtiny24A/44A/84A Figure 21-44. Bandgap Voltage vs. Supply Voltage 1,2 1,18 1,16 Bandgap Voltage (V) 1,14 1,12 1,1 1,08 1,06 1,04 1,02 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 Vcc (V) Figure 21-45. Bandgap Voltage vs.
Figure 21-46. VIH: Input Threshold Voltage vs. VCC Reset Pin, Read as ‘1’ 2,5 Threshold (V) 2 1,5 -40 °C 25 °C 85 °C 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-47. VIL: Input Threshold Voltage vs.
ATtiny24A/44A/84A Figure 21-48. VIH-VIL: Input Hysteresis vs. VCC Reset Pin 1 0,9 0,8 Input Hysteresis (V) 0,7 -40 °C 0,6 0,5 25 °C 0,4 0,3 85 °C 0,2 0,1 0 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-49. Minimum Reset Pulse Width vs.
21.2.10 Analog Comparator Offset Figure 21-50. Analog Comparator Offset VCC = 5V 0.004 0.002 0 Offset (V) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.002 -0.004 -40 25 -0.006 85 -0.008 VIN (V) 21.2.11 Internal Oscillator Speed Figure 21-51. Watchdog Oscillator Frequency vs.
ATtiny24A/44A/84A Figure 21-52. Watchdog Oscillator Frequency vs. Temperature 124 122 FRC (kHz) 120 118 1.8 V 116 3.0 V 114 5.5 V 112 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 21-53. Calibrated 8 MHz RC Oscillator Frequency vs.
Figure 21-54. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8,4 8,3 5.5 V 8,2 3.0 V FRC (MHz) 8,1 1.8 V 8 7,9 7,8 7,7 7,6 7,5 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 21-55. Calibrated 8 MHz RC Oscillator Frequency vs.
ATtiny24A/44A/84A 21.3 21.3.1 ATtiny44A Current Consumption in Active Mode Figure 21-56. Active Supply Current vs. Low Frequency 0.1 - 1.0 MHz, PRR = 0xFF 1 5.5 V 5.0 V 0.8 4.5 V 0.6 I CC (mA) 4.0 V 3.3 V 0.4 2.7 V 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 21-57. Active Supply Current vs. frequency 1 - 20 MHz, PRR = 0xFF 12 5.5 V 10 5.0 V 4.5 V I CC (mA) 8 6 4.0 V 4 3.3 V 2.7 V 2 1.
Figure 21-58. Active Supply Current vs. VCC Internal RC Oscillator, 8 MHz 6 85 °C 25 °C -40 °C 5 I CC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 21-59. Active Supply Current vs. VCC Internal RC Oscillator, 1 MHz 1.2 85 °C 25 °C -40 °C 1 I CC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24A/44A/84A Figure 21-60. Active Supply Current vs. VCC Internal RC Oscillator, 128 kHz 0.14 -40 °C 25 °C 85 °C 0.12 I CC (mA) 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 21.3.2 Current Consumption in Idle Mode Figure 21-61. Idle Supply Current vs. Low Frequency 0.1 - 1.0 MHz, PRR = 0xFF 0.2 0.18 5.5 V 0.16 5.0 V 0.14 4.5 V I CC (mA) 0.12 4.0 V 0.1 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 21-62. Idle Supply Current vs. Frequency 1 - 20 MHz, PRR = 0xFF I CC (mA) 4 3.5 5.5 V 3 5.0 V 2.5 4.5 V 2 4.0 V 1.5 1 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 21-63. Idle Supply Current vs. VCC Internal RC Oscillator, 8 MHz 2 1.8 1.6 85 °C 25 °C -40 °C 1.4 I CC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24A/44A/84A Figure 21-64. Idle Supply Current vs. VCC Internal RC Oscillator, 1 MHz 0.4 85 °C 25 °C -40 °C 0.35 0.3 I CC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 21-65. Idle Supply Current vs. VCC Internal RC Oscillator, 128 kHz 0.03 -40 °C 25 °C 85 °C 0.025 I CC (mA) 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
21.3.3 Standby Supply Current Figure 21-66. Standby Supply Current vs. VCC 4 MHz External Crystal, 22 pF External Capacitors, Watchdog Timer Disabled 0.1 85 °C 0.08 25 °C -40 °C I CC (mA) 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 21.3.4 Current Consumption in Power-down Mode Figure 21-67. Power-down Supply Current vs. VCC Watchdog Timer Disabled 1.4 85 °C 1.2 I CC (uA) 1 0.8 0.6 0.4 25 °C 0.2 -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24A/44A/84A Figure 21-68. Power-down Supply Current vs. VCC Watchdog Timer Enabled 10 8 -40 °C 85 °C 25 °C I CC (uA) 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 21.3.5 Current Consumption in Reset Figure 21-69. Reset Supply Current vs. VCC 0.1 - 1.0 MHz, Excluding Current through Reset Pull-up 0.16 5.5 V 0.14 5.0 V 0.12 4.5 V I CC (mA) 0.1 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 21-70. Reset Supply Current vs. VCC 1 - 20 MHz, Excluding Current Through Reset Pull-up 3 5.5 V 2.5 5.0 V 4.5 V I CC (mA) 2 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 21.3.6 Current Consumption of Peripheral Units Figure 21-71. ADC Current vs. VCC 4 MHz Frequency 600 500 I CC (uA) 400 300 200 100 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24A/44A/84A Figure 21-72. AREF Pin Current vs. Pin Voltage 180 160 AREF pin current (uA) 140 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 AREF (V) Figure 21-73. Analog Comparator Current vs. VCC 4 MHz Frequency 160 140 120 I CC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 21-74. Programming Current vs. VCC 12000 -40 °C 10000 I CC (uA) 8000 25 °C 6000 85 °C 4000 2000 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 21-75. Brownout Detector Current vs. VCC BOD Level = 1.8V 35 30 I CC (uA) 25 85 °C 25 °C -40 °C 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24A/44A/84A Figure 21-76. Watchdog Timer Current vs. VCC 0.008 -40 °C 0.007 25 °C 85 °C 0.006 I CC (mA) 0.005 0.004 0.003 0.002 0.001 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 21.3.7 Pull-up Resistors Figure 21-77. Pull-up Resistor Current vs. Input Voltage I/O Pin, VCC = 1.8V 50 40 I OP (uA) 30 20 10 25 °C 85 °C -40 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 21-78. Pull-up Resistor Current vs. Input Voltage I/O Pin, VCC = 2.7V 80 70 60 I OP (uA) 50 40 30 20 10 25 °C 85 °C -40 °C 0 0 0.5 1 1.5 2 2.5 3 V OP (V) Figure 21-79. Pull-up Resistor Current vs.
ATtiny24A/44A/84A Figure 21-80. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 1.8V 40 35 30 I RESET (uA) 25 20 15 10 5 85 °C 25 °C -40 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 V RESET (V) Figure 21-81. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 2.7V 60 50 I RESET (uA) 40 30 20 10 85 °C 25 °C -40 °C 0 0 0.5 1 1.5 2 2.
Figure 21-82. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 5V 120 100 I RESET (uA) 80 60 40 20 85 °C 25 °C -40 °C 0 0 1 2 3 4 5 V RESET (V) 21.3.8 Output Driver Strength Figure 21-83. VOL: Output Voltage vs. Sink Current I/O Pin, VCC = 3V 1.2 1 85 °C 0.8 V OL (V) 25 °C 0.6 -40 °C 0.4 0.
ATtiny24A/44A/84A Figure 21-84. VOL: Output Voltage vs. Sink Current I/O Pin, VCC = 5V 0.7 0.6 85 °C 0.5 V OL (V) 25 °C 0.4 -40 °C 0.3 0.2 0.1 0 0 5 10 15 20 I OL (mA) Figure 21-85. VOH: Output Voltage vs. Source Current I/O Pin, VCC = 3V 3.2 3 V OH (V) 2.8 2.6 2.4 -40 °C 2.2 25 °C 2 85 °C 1.
Figure 21-86. VOH: Output Voltage vs. Source Current I/O Pin, VCC = 5V 5.2 5 V OH (V) 4.8 4.6 -40 °C 25 °C 4.4 85 °C 4.2 0 5 10 15 20 I OH (mA) Figure 21-87. VOL: Output Voltage vs. Sink Current Reset Pin as I/O, VCC = 3V 1.4 1.2 85 °C V OL (V) 1 25 °C 0.8 0.6 -40 °C 0.4 0.2 0 0 0.5 1 1.5 2 2.
ATtiny24A/44A/84A Figure 21-88. VOL: Output Voltage vs. Sink Current Reset Pin as I/O, VCC = 5V 2 85 °C 1.8 1.6 1.4 25 °C V OL (V) 1.2 1 -40 °C 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 8 I OL (mA) Figure 21-89. VOH: Output Voltage vs. Source Current Reset Pin as I/O, VCC = 3V 3 2.5 V OH (V) 2 1.5 -40 °C 1 25 °C 85 °C 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 21-90. VOH: Output Voltage vs. Source Current Reset Pin as I/O, VCC = 5V 5 4.5 4 3.5 V OH (V) 3 -40 °C 25 °C 85 °C 2.5 2 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 I OH (mA) 21.3.9 Input Threshold and Hysteresis (for I/O Ports) Figure 21-91. VIH: Input Threshold Voltage vs. VCC IO Pin, Read as ‘1’ 3.5 -40 °C 25 °C 85 °C 3 Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24A/44A/84A Figure 21-92. VIL: Input Threshold Voltage vs. VCC I/O Pin, Read as ‘0’ 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 21-93. VIH-VIL: Input Hysteresis vs. VCC I/O Pin 0.8 0.7 Input Hysteresis (V) 0.6 -40 °C 25 °C 85 °C 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 21-94. VIH: Input Threshold Voltage vs. VCC Reset Pin as I/O, Read as ‘1’ 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 21-95. VIL: Input Threshold Voltage vs. VCC Reset Pin as I/O, Read as ‘0’ 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24A/44A/84A Figure 21-96. VIH-VIL: Input Hysteresis vs. VCC Reset Pin as I/O 1 0.9 0.8 -40 °C Input Hysteresis (V) 0.7 0.6 25 °C 0.5 85 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 21.3.10 BOD, Bandgap and Reset Figure 21-97. BOD Threshold vs. Temperature BODLEVEL is 4.3V 4.36 4.34 4.32 RISING VCC Threshold (V) 4.3 4.28 4.26 4.24 FALLING VCC 4.22 4.
Figure 21-98. BOD Threshold vs. Temperature BODLEVEL is 2.7V 2.78 2.76 2.74 Threshold (V) RISING VCC 2.72 2.7 2.68 FALLING VCC 2.66 2.64 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 21-99. BOD Threshold vs. Temperature BODLEVEL is 1.8V 1.84 1.83 Threshold (V) 1.82 RISING VCC 1.81 1.8 1.79 1.78 FALLING VCC 1.
ATtiny24A/44A/84A Figure 21-100. Bandgap Voltage vs. Supply Voltage 1.2 1.18 1.16 Bandgap Voltage (V) 1.14 1.12 1.1 1.08 1.06 1.04 1.02 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 21-101. Bandgap Voltage vs. Temperature 1.2 1.18 1.16 Bandgap Voltage (V) 1.14 1.12 1.1 1.08 1.06 1.04 1.
Figure 21-102. VIH: Input Threshold Voltage vs. VCC Reset Pin, Read as ‘1’ 2,5 Threshold (V) 2 1,5 -40 °C 25 °C 85 °C 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-103. VIL: Input Threshold Voltage vs.
ATtiny24A/44A/84A Figure 21-104. VIH-VIL: Input Hysteresis vs. VCC Reset Pin 1 0.9 0.8 Input Hysteresis (V) 0.7 0.6 -40 °C 0.5 25 °C 0.4 0.3 85 °C 0.2 0.1 0 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 21-105. Minimum Reset Pulse Width vs. VCC 2000 1800 1600 Pulsewidth (ns) 1400 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
21.3.11 Analog Comparator Offset Figure 21-106. Analog Comparator Offset VCC = 5V 0.004 0.003 0.002 0.001 0 Offset (V) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -0.001 -0.002 -0.003 -0.004 -40 25 -0.005 85 -0.006 -0.007 VIN (V) 21.3.12 Internal Oscillator Speed Figure 21-107. Watchdog Oscillator Frequency vs. VCC 0.12 0.118 -40 °C Frequency (MHz) 0.116 25 °C 0.114 0.112 0.11 85 °C 0.108 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny24A/44A/84A Figure 21-108. Watchdog Oscillator Frequency vs. Temperature 0.12 0.118 Frequency (MHz) 0.116 0.114 1.8 V 0.112 3.0 V 0.11 5.5 V 0.108 0.106 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 21-109. Calibrated 8 MHz RC Oscillator Frequency vs. VCC 8.4 8.2 Frequency (MHz) 85 °C 25 °C 8 -40 °C 7.8 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 21-110. Calibrated 8 MHz RC oscillator Frequency vs. Temperature 8.2 5.0 V 3.0 V 8.1 8 Frequency (MHz) 1.8 V 7.9 7.8 7.7 7.6 7.5 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 21-111. Calibrated 8 MHz RC Oscillator Frequency vs.
ATtiny24A/44A/84A 21.4 21.4.1 ATtiny84A Current Consumption in Active Mode Figure 21-112. Active Supply Current vs. Low Frequency 0.1 - 1.0 MHz, PRR = 0xFF 1 5.5 V 0,8 5.0 V 4.5 V 0,6 ICC (mA) 4.0 V 3.3 V 0,4 2.7 V 0,2 1.8 V 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 21-113. Active Supply Current vs. Frequency 1 - 20 MHz, PRR = 0xFF 12 10 5.5 V 5.0 V 8 ICC (mA) 4.5 V 6 4.0 V 4 3.3 V 2.7 V 2 1.
Figure 21-114. Active Supply Current vs. VCC Internal RC Oscillator, 8 MHz 5 85 °C 25 °C -40 °C 4,5 4 3,5 ICC (mA) 3 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-115. Active Supply Current vs.
ATtiny24A/44A/84A Figure 21-116. Active Supply Current vs. VCC Internal RC Oscillator, 128 kHz 0,14 0,12 -40 °C 25 °C 85 °C 0,1 ICC (mA) 0,08 0,06 0,04 0,02 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 21.4.2 Current Consumption in Idle Mode Figure 21-117. Idle Supply Current vs. Low Frequency 0.1 - 1.0 MHz, PRR = 0xFF 0,14 5.5 V 0,12 5.0 V 0,1 4.5 V 4.0 V 0,06 3.3 V ICC (mA) 0,08 2.7 V 0,04 1.
Figure 21-118. Idle Supply Current vs. Frequency 1 - 20 MHz, PRR = 0xFF 4 3,5 3 5.5 V ICC (mA) 2,5 5.0 V 2 4.5 V 1,5 4.0 V 1 3.3 V 0,5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 21-119. Idle Supply Current vs.
ATtiny24A/44A/84A Figure 21-120. Idle Supply Current vs. VCC Internal RC Oscillator, 1 MHz 0,4 0,35 0,3 85 °C 25 °C -40 °C ICC (mA) 0,25 0,2 0,15 0,1 0,05 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-121. Idle Supply Current vs.
21.4.3 Current Consumption in Power-down Mode Figure 21-122. Power-down Supply Current vs. VCC Watchdog Timer Disabled 1,6 1,4 85 °C 1,2 ICC (uA) 1 0,8 0,6 0,4 25 °C 0,2 -40 °C 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 4 4,5 5 5,5 VCC (V) Figure 21-123. Power-down Supply Current vs.
ATtiny24A/44A/84A 21.4.4 Current Consumption in Reset Figure 21-124. Reset Supply Current vs. VCC 0.1 - 1.0 MHz, Excluding Current through Reset Pull-up 0,16 0,14 0,12 5.5 V ICC (mA) 0,1 5.0 V 4.5 V 0,08 4.0 V 0,06 3.3 V 2.7 V 0,04 1.8 V 0,02 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 21-125. Reset Supply Current vs. VCC 1 - 20 MHz, Excluding Current through Reset Pull-up 3 2,5 ICC (mA) 2 5.5 V 5.0 V 1,5 4.5 V 4.0 V 1 3.3 V 0,5 2.7 V 1.
21.4.5 Current Consumption of Peripheral Units Figure 21-126. ADC Current vs. VCC 4 MHz Frequency 600 500 ICC (uA) 400 300 200 100 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 4 4,5 5 5,5 VCC (V) Figure 21-127. AREF Pin Current vs.
ATtiny24A/44A/84A Figure 21-128. Analog Comparator Current vs. VCC 4 MHz Frequency 160 140 120 ICC (uA) 100 80 60 40 20 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-129. Programming Current vs.
Figure 21-130. Brownout Detector Current vs. VCC BOD Level = 1.8V 45 40 35 ICC (uA) 30 25 85 °C 25 °C -40 °C 20 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 21.4.6 Pull-up Resistors Figure 21-131. Pull-up Resistor Current vs. Input Voltage I/O Pin, VCC = 1.
ATtiny24A/44A/84A Figure 21-132. Pull-up Resistor Current vs. Input Voltage I/O Pin, VCC = 2.7V 80 70 60 IOP (uA) 50 40 30 20 10 25 °C 85 °C -40 °C 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 21-133. Pull-up Resistor Current vs.
Figure 21-134. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 1.8V 40 35 30 IRESET (uA) 25 20 15 10 5 25 °C -40 °C 85 °C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET (V) Figure 21-135. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 2.
ATtiny24A/44A/84A Figure 21-136. Reset Pull-up Resistor Current vs. Reset Pin Voltage VCC = 5V 120 100 IRESET (uA) 80 60 40 20 25 °C -40 °C 85 °C 0 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 VRESET (V) 21.4.7 Output Driver Strength Figure 21-137. VOL: Output Voltage vs.
Figure 21-138. VOL: Output Voltage vs. Sink Current I/O Pin, VCC = 5V 0,7 0,6 85 °C 0,5 25 °C -40 °C VOL (V) 0,4 0,3 0,2 0,1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 21-139. VOH: Output Voltage vs.
ATtiny24A/44A/84A Figure 21-140. VOH: Output Voltage vs. Source Current I/O Pin, VCC = 5V 5,2 5 VOH (V) 4,8 4,6 -40 °C 25 °C 4,4 85 °C 4,2 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 21-141. VOL: Output Voltage vs.
Figure 21-142. VOL: Output Voltage vs. Sink Current Reset Pin as I/O, VCC = 5V 2 85 °C 1,8 1,6 25 °C 1,4 VOL (V) 1,2 -40 °C 1 0,8 0,6 0,4 0,2 0 0 1 2 3 4 5 6 7 8 IOL (mA) Figure 21-143. VOH: Output Voltage vs.
ATtiny24A/44A/84A Figure 21-144. VOH: Output Voltage vs. Source Current Reset Pin as I/O, VCC = 5V 5 4,5 4 3,5 VOH (V) 3 -40 °C 25 °C 85 °C 2,5 2 1,5 1 0,5 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 IOH (mA) 21.4.8 Input Threshold and Hysteresis (for I/O Ports) Figure 21-145. VIH: Input Threshold Voltage vs.
Figure 21-146. VIL: Input Threshold Voltage vs. VCC I/O Pin, Read as ‘0’ 2,5 85 °C 25 °C -40 °C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-147. VIH-VIL: Input Hysteresis vs.
ATtiny24A/44A/84A Figure 21-148. VIH: Input Threshold Voltage vs. VCC Reset Pin as I/O, Read as ‘1’ 3 25 °C 85 °C -40 °C 2,5 Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-149. VIL: Input Threshold Voltage vs.
Figure 21-150. VIH-VIL: Input Hysteresis vs. VCC Reset Pin as I/O 1 0,9 0,8 Input Hysteresis (V) 0,7 85 °C 0,6 25 °C 0,5 -40 °C 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 21.4.9 BOD, Bandgap and Reset Figure 21-151. BOD Threshold vs. Temperature BODLEVEL is 4.
ATtiny24A/44A/84A Figure 21-152. BOD Threshold vs. Temperature BODLEVEL is 2.7V 2,82 2,8 RISING VCC 2,78 Threshold (V) 2,76 2,74 FALLING VCC 2,72 2,7 2,68 2,66 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 21-153. Bandgap Voltage vs.
Figure 21-154. Bandgap Voltage vs. Temperature 1,2 1,18 1,16 Bandgap Voltage (V) 1,14 1,12 1,1 1,08 1,06 1,04 1,02 1 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 21-155. VIH: Input Threshold Voltage vs.
ATtiny24A/44A/84A Figure 21-156. VIL: Input Threshold Voltage vs. VCC Reset Pin, Read as ‘0’ 2,5 85 °C 25 °C -40 °C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 4 4,5 5 5,5 VCC (V) Figure 21-157. VIH-VIL: Input Hysteresis vs.
Figure 21-158. Minimum Reset Pulse Width vs. VCC 2000 1800 1600 Pulsewidth (ns) 1400 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 21.4.10 Analog Comparator Offset Figure 21-159. Analog Comparator Offset VCC = 5V 0.004 0.002 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Offset (V) -0.002 -0.004 -0.006 -40 25 -0.008 85 -0.01 -0.
ATtiny24A/44A/84A 21.4.11 Internal Oscillator Speed Figure 21-160. Watchdog Oscillator Frequency vs. VCC 120 118 116 FRC (kHz) -40 °C 114 25 °C 112 110 85 °C 108 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-161. Watchdog Oscillator Frequency vs. Temperature 120 118 FRC (kHz) 116 114 112 1.8 V 3.0 V 110 5.
Figure 21-162. Calibrated 8 MHz RC Oscillator Frequency vs. VCC 8,4 8,3 85 °C 8,2 25 °C 8,1 -40 °C FRC (MHz) 8 7,9 7,8 7,7 7,6 7,5 7,4 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 21-163. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8,4 8,3 8,2 5.0 V 8,1 FRC (MHz) 3.0 V 8 1.
ATtiny24A/44A/84A Figure 21-164. Calibrated 8 MHz RC Oscillator Frequency vs.
22.
ATtiny24A/44A/84A Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
23.
ATtiny24A/44A/84A Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
24. Ordering Information 24.1 ATtiny24A Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) ATtiny24A-SSU 14S1 ATtiny24A-SSUR 14P3 ATtiny24A-PU ATtiny24A-CCU Industrial (-40°C to +85°C) (5) 15CC1 ATtiny24A-CCUR ATtiny24A-MU 20M1 ATtiny24A-MUR ATtiny24A-MMH (4) 20M2 20 1.8 – 5.
ATtiny24A/44A/84A 24.2 ATtiny44A Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) ATtiny44A-SSU 14S1 ATtiny44A-SSUR 14P3 ATtiny44A-PU ATtiny44A-CCU Industrial (-40°C to +85°C) (5) 15CC1 ATtiny44A-CCUR ATtiny44A-MU 20M1 ATtiny44A-MUR 20 ATtiny44A-MMH (4) 1.8 – 5.
24.3 ATtiny84A Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) ATtiny84A-SSU 14S1 ATtiny84A-SSUR 14P3 ATtiny84A-PU ATtiny84A-CCU Industrial (-40°C to +85°C) (5) 20 15CC1 ATtiny84A-CCUR ATtiny84A-MU 1.8 – 5.5V 20M1 ATtiny84A-MUR ATtiny84A-MMH (4) 20M2 Industrial (-40°C to +125°C) (7) Notes: ATtiny84A-MMHR (4) ATtiny84A-SSF 14S1 ATtiny84A-SSFR 1. For speed vs. supply voltage, see section 20.3 “Speed” on page 174. 2.
ATtiny24A/44A/84A 25. Packaging Information 25.1 14S1 1 E H E N L Top View End View e COMMON DIMENSIONS (Unit of Measure = mm/inches) b SYMBOL A1 A D Side View NOM MAX – 1.75/0.0688 NOTE 1.35/0.0532 A1 0.1/.0040 – 0.25/0.0098 b 0.33/0.0130 – 0.5/0.0200 5 D 8.55/0.3367 – 8.74/0.3444 2 E 3.8/0.1497 – 3.99/0.1574 3 H 5.8/0.2284 – 6.19/0.2440 L 0.41/0.0160 – 1.27/0.0500 e Notes: MIN A 4 1.27/0.050 BSC 1.
25.2 14P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 5.334 A1 0.381 – – D 18.669 – 19.685 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.143 – 1.778 L 2.921 – 3.810 C 0.203 – 0.
ATtiny24A/44A/84A 25.3 15CC1 1 2 3 4 0.08 A Pin#1 ID B SIDE VIEW D C D b1 A1 E A A2 TOP VIEW E1 15-Øb e D e COMMON DIMENSIONS (Unit of Measure = mm) C D1 B SYMBOL A MIN NOM MAX A – – 0.60 A1 0.12 – – b 0.25 0.30 0.35 1 b1 0.25 – – 2 D 2.90 3.00 3.10 0.38 REF A2 A1 BALL CORNER 1 2 3 4 BOTTOM VIEW 1.95 BSC D1 E Note1: Dimension “b” is measured at the maximum ball dia. in a plane parallel E1 e to the seating plane.
25.4 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b 0.18 D D2 E2 L MAX NOTE 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOM 0.20 REF E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
ATtiny24A/44A/84A 25.5 20M2 D C y Pin 1 ID E SIDE VIEW TOP VIEW A1 A D2 16 17 18 19 20 COMMON DIMENSIONS (Unit of Measure = mm) C0.18 (8X) 15 Pin #1 Chamfer (C 0.3) 14 2 e E2 13 3 12 4 11 5 MIN NOM MAX A 0.75 0.80 0.85 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 SYMBOL 1 C b 10 9 8 7 6 K L BOTTOM VIEW 0.3 Ref (4x) NOTE 0.152 D 2.90 3.00 3.10 D2 1.40 1.55 1.70 E 2.90 3.00 3.10 E2 1.40 1.55 1.70 e – 0.45 – L 0.35 0.40 0.45 K 0.20 – – y 0.
26. Errata The revision letters in this section refer to the revision of the corresponding ATtiny24A/44A/84A device. 26.1 26.1.1 ATtiny24A Rev. H No known errata. 26.1.2 Rev. G Not sampled. 26.1.3 Rev. F Not sampled. 26.2 ATtiny44A 26.2.1 Rev. G No known errata. Yield improvement. 26.2.2 Rev. F No known errata. 26.2.3 Rev. E Not sampled. 26.3 26.3.1 ATtiny84A Rev. C No known errata.
ATtiny24A/44A/84A 27. Datasheet Revision History 27.1 Rev. 8183F – 06/12 1. Updated: – Table 16-1 on page 138 – Figure 16-7 on page 137 – “Ordering Information” on page 270 27.2 Rev. 8183E – 01/12 1. Updated: – Production status for ATtiny24A and ATtiny84A – “Start Condition Detector” on page 122 – “Ordering Information” on page 270, 271, and 272 27.3 Rev. 8183D – 04/11 1. Added errata for ATtiny44A rev. G in Section 26. “Errata” on page 278 27.4 Rev. 8183C – 03/11 1.
– Section 24. “Ordering Information” on page 270, added tape & reel and topside marking, updated notes 5. Updated Figures: – Figure 4-1 “Block Diagram of the AVR Architecture” on page 7 – Figure 8-1 “Reset Logic” on page 38 – Figure 14-1 “Universal Serial Interface, Block Diagram” on page 116, USIDB -> USIBR – Figure 19-5 “High-voltage Serial Programming Waveforms” on page 169 6.
ATtiny24A/44A/84A Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 Pin Descriptions .................................................................................................3 2 Overview ...................................................................................................
8 9 7.1 Sleep Modes ....................................................................................................33 7.2 Software BOD Disable .....................................................................................34 7.3 Power Reduction Register ...............................................................................35 7.4 Minimizing Power Consumption ......................................................................35 7.5 Register Description .......................
ATtiny24A/44A/84A 12.5 Input Capture Unit ...........................................................................................88 12.6 Output Compare Units .....................................................................................90 12.7 Compare Match Output Unit ............................................................................92 12.8 Modes of Operation .........................................................................................94 12.
17 debugWIRE On-chip Debug System .................................................. 150 17.1 Features ........................................................................................................150 17.2 Overview ........................................................................................................150 17.3 Physical Interface ..........................................................................................150 17.4 Software Break Points ...........................
ATtiny24A/44A/84A 21 Typical Characteristics ........................................................................ 182 21.1 Supply Current of I/O Modules ......................................................................182 21.2 ATtiny24A ......................................................................................................183 21.3 ATtiny44A ......................................................................................................211 21.4 ATtiny84A .................
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