Datasheet

92
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
Figure 14-1. 16-bit Timer/Counter Block Diagram
(1)
Note: 1. See Figure 1-1 on page 2 for Timer/Counter1 pin placement and description.
14.2.1 Registers
The timer/counter (TCNT1), output compare registers (OCR1A/B), and input capture register
(ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit
registers. These procedures are described in the section “Accessing 16-bit Registers” on page
94. The timer/counter control registers (TCCR1A/B) are 8-bit registers, and have no CPU
access restrictions. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visi-
ble in the timer interrupt flag register (TIFR). All interrupts are individually masked with the
timer interrupt mask register (TIMSK). TIFR and TIMSK are not shown in the figure.
The timer/counter can be clocked internally, via the prescaler, or by an external clock source
on the T1 pin. The clock select logic block controls which clock source and edge the
timer/counter uses to increment (or decrement) its value. The timer/counter is inactive when
no clock source is selected. The output from the clock select logic is referred to as the timer
clock (clk
T
1
).
Clock Select
Timer/Counter
DATA BUS
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn