Datasheet

89
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
13.9.6 TIMSK0 – Timer/Counter 0 Interrupt Mask Register
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 2- OCIE0B: Timer/Counter 0 Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the status register is set, the timer/coun-
ter 0 compare match B interrupt is enabled. The corresponding interrupt is executed if a
compare match in timer/counter occurs, i.e., when the OCF0B bit is set in the timer/counter 0
interrupt flag register (TIFR0).
• Bit 1– OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the status register is set, the timer/coun-
ter 0 compare match A interrupt is enabled. The corresponding interrupt is executed if a
compare match in timer/counter 0 occurs, i.e., when the OCF0A bit is set in the timer/counter
0 interrupt flag register (TIFR0).
• Bit 0– TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the status register is set, the timer/counter
0 overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in
timer/counter 0 occurs, i.e., when the TOV0 bit is set in the timer/counter 0 interrupt flag regis-
ter (TIFR0).
13.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 2– OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a compare match occurs between the timer/counter 0 and the data
in OCR0B, the output compare register 0 B. OCF0B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logi-
cal one to the flag. When the I-bit in SREG, OCIE0B (timer/counter compare b match interrupt
enable), and OCF0B are set, the timer/counter compare match interrupt is executed.
• Bit 1– OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a compare match occurs between the timer/counter 0 and the data
in OCR0A, the output compare register 0 A. OCF0A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logi-
cal one to the flag. When the I-bit in SREG, OCIE0A (timer/counter 0 compare match interrupt
enable), and OCF0A are set, the timer/counter 0 compare match interrupt is executed.
Bit 76543210
0x39 (0x59) – – – – – OCIE0B OCIE0A TOIE0 TIMSK0
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x38 (0x58) – – – – – OCF0B OCF0A TOV0 TIFR0
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0