Datasheet
87
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
13.9.2 TCCR0B – Timer/Counter Control Register B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to logical zero
when TCCR0B is written when operating in PWM mode. When writing a logical one to the
FOC0A bit, an immediate compare match is forced on the waveform generation unit. The
OC0A output is changed according to its COM0A1:0 bit settings. Note that the FOC0A bit is
implemented as a strobe. Therefore, it is the value present in the COM0A1:0 bits that deter-
mines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to logical zero
when TCCR0B is written when operating in PWM mode. When writing a logical one to the
FOC0B bit, an immediate compare match is forced on the waveform generation unit. The
OC0B output is changed according to its COM0B1:0 bit settings. Note that the FOC0B bit is
implemented as a strobe. Therefore, it is the value present in the COM0B1:0 bits that deter-
mines the effect of the forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84, and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the “TCCR0A – Timer/Counter Control Register A” on page 84.
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Bit 7 6 5 4 3 2 1 0
0x33 (0x53)
FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B
Read/Write W W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0