Datasheet

82
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
• OCR0A changes its value from MAX, as in Figure 13-7 on page 81. When the OCR0A value
is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of
an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
misses the compare match and, hence, the OCn change that would have happened on the
way up.
13.8 Timer/Counter Timing Diagrams
The timer/counter is a synchronous design, and the timer clock (clkT0) is, therefore, shown as
a clock enable signal in the following figures. The figures include information on when interrupt
flags are set. Figure 13-8 on page 82 contains timing data for basic timer/counter opera-
tion.The figure shows the count sequence close to the max value in all modes other than
phase correct PWM mode.
Figure 13-8. Timer/Counter Timing Diagram, no Prescaling
Figure 13-9 on page 82 shows the same timing data, but with the prescaler enabled.
Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 13-10 on page 83 shows the setting of OCF0B in all modes and OCF0A in all modes
except CTC mode and PWM mode, where OCR0A is TOP.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)