Datasheet

7701F–AVR–10/12

Atmel ATtiny24/44/84 [Preliminary]

This high frequency makes the fast PWM mode well suited for power regulation, rectification,

and DAC applications. High frequency allows the use of physically smaller external compo-

nents (coils, capacitors, etc.), and hence reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 13-6 on page 79. The TCNT0 value is in the timing diagram

shown as a histogram for illustrating the single-slope operation. The diagram includes

non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes

represent Compare Matches between OCR0x and TCNT0.

Figure 13-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the

interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.

Setting the COM0x1:0 bits to two will produce a non-inverted PWM, and an inverted PWM out-

put can be generated by setting the COM0x1:0 bits to three. Setting the COM0A1:0 bits to one

allows the AC0A pin to toggle on compare matches if the WGM02 bit is set. This option is not

available for the OC0B pin (See Table 13-3 on page 84). The actual OC0x value will only be

visible on the port pin if the data direction for the port pin is set as output. The PWM waveform

is generated by setting (or clearing) the OC0x register at the compare match between OCR0x

and TCNT0, and clearing (or setting) the OC0x register at the timer clock cycle when the coun-

ter is cleared (changes from top to bottom).

The PWM frequency for the output can be calculated by the following equation:

The variable N represents the prescale factor (1, 8, 64, 256, or 1024)..

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period

2 3

OCn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

4 5 6 7

OCnxPWM

clk_I/O

N 256⋅

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