Datasheet

73
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when
no clock source is selected. The output from the Clock Select logic is referred to as the timer
clock (clk
T0
).
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform
Generator to generate a PWM or variable frequency output on the Output Compare pins
(OC0A and OC0B). See “Output Compare Unit” on page 74 for details. The Compare Match
event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an
Output Compare interrupt request.
13.2.2 Definitions
Many register and bit references in this section are written in general form. A lower case "n"
replaces the timer/counter number, in this case 0. A lower case "x" replaces the output com-
pare unit, in this case compare unit A or compare unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing timer/coun-
ter 0 counter value and so on.
The definitions in Table 13-1 on page 73 are also used extensively throughout the document.
Table 13-1. Definitions
13.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0)
bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources
and prescaler, see “Timer/Counter Prescaler” on page 120.
13.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Fig-
ure 13-2 on page 73 shows a block diagram of the counter and its surroundings.
Figure 13-2. Counter Unit Block Diagram
BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in
the count sequence. The TOP value can be assigned to be the fixed value
0xFF (MAX) or the value stored in the OCR0A Register. The assignment is
dependent on the mode of operation.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn
bottom
direction
clear