Datasheet

72
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
13. 8-bit Timer/Counter0 with PWM
13.1 Features
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• Clear Timer on Compare Match (Auto Reload)
• Glitch Free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
13.2 Overview
Timer/counter 0 is a general purpose 8-bit timer/counter module, with two independent out-
put compare units, and with PWM support. It allows accurate program execution timing (event
management) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 13-1 on page 72. For
the actual placement of I/O pins, refer to Figure 1-1 on page 2. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the “Register Description” on page 84.
Figure 13-1. 8-bit Timer/Counter Block Diagram
13.2.1 Registers
The timer/counter (TCNT0) and output compare registers (OCR0A and OCR0B) are 8-bit reg-
isters. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
timer/counter 0 interrupt flag register (TIFR0). All interrupts are individually masked with the
timer interrupt mask register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source
on the T0 pin. The Clock Select logic block controls which clock source and edge the
Clock Select
Timer/Counter
DATA BUS
OCRnA
OCRnB
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
=
Fixed
TOP
Value
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TCCRnA TCCRnB
Tn
Edge
Detector
( From Prescaler )
clk
Tn