Datasheet

7
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
5. CPU Core
5.1 Overview
This section discusses the Atmel
®
AVR
®
core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must, therefore, be able to access
memories, perform calculations, control peripherals, and handle interrupts.
5.2 Architectural Overview
Figure 5-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR
®
uses a Harvard architecture, with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single-level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the program memory. This concept enables instructions to be
executed in every clock cycle. The program memory is in-system reprogrammable flash
memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
Timer/Counter 0
Timer/Counter 1
Universal
Serial Interface