Datasheet

69
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
• Port B, Bit 3 – RESET/dW/PCINT11
RESET
: External Reset input is active low and enabled by un-programming ("1") the RST-
DISBL fuse. Pull-up is activated and output driver and digital input are deactivated when the
pin is used as the RESET
pin.
dW: When the debugWIRE enable (DWEN) fuse is programmed and lock bits are un-pro-
grammed, the debugWIRE system within the target device is activated. The RESET port pin is
configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes
the communication gateway between target and emulator.
PCINT11: Pin change interrupt source 11. The PB3 pin can serve as an external interrupt
source for pin change interrupt 1.
Table 12-8 on page 69 and Table 12-9 on page 70 relate the alternate functions of Port B to
the overriding signals shown in Figure 12-5 on page 62.
Table 12-8. Overriding Signals for Alternate Functions in PB3..PB2
Signal
Name
PB3/RESET/dW/
PCINT11 PB2/INT0/OC0A/CKOUT/PCINT10
PUOE RSTDISBL
(1)
+ DEBUGWIRE_ENABLE
(2)
1. RSTDISBL is 1 when the Fuse is “0” (Programmed).
2. DebugWIRE is enabled when DWEN fuse is programmed and lock bits are un-programmed.
CKOUT
PUOV 1 0
DDOE RSTDISBL
(1)
+ DEBUGWIRE_ENABLE
(2)
CKOUT
DDOV
DEBUGWIRE_ENABLE
(2)
• debugWire
Tra ns mi t
1'b1
PVOE RSTDISBL
(1)
+ DEBUGWIRE_ENABLE
(2)
CKOUT + OC0A enable
PVOV 0 CKOUT • System Clock + CKOUT
• OC0A
PTOE 0 0
DIEOE
RSTDISBL
(1)
+ DEBUGWIRE_ENABLE
(2)
+ PCINT11 • PCIE1
PCINT10 • PCIE1 + INT0
DIEOV
DEBUGWIRE_ENABLE
(2)
+ (RSTDISBL
(1)
• PCINT11 • PCIE1)
PCINT10 • PCIE1 + INT0
DI dW/PCINT11 Input INT0/PCINT10 Input
AIO