Datasheet

7701F–AVR–10/12

Atmel ATtiny24/44/84 [Preliminary]

If PORTxn is written logical one when the pin is configured as an output pin, the port pin is

driven high (one). If PORTxn is written logical zero when the pin is configured as an output pin,

the port pin is driven low (zero).

12.2.2 Toggling the Pin

Writing a logical one to PINxn toggles the value of PORTxn, independent on the value of

DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

12.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,

PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01)

or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully

acceptable, as a high-impedance environment will not notice the difference between a strong

high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR register can be set

to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn,

PORTxn} = 0b10) as an intermediate step.

Table 12-1 on page 58 summarizes the control signals for the pin value.

12.2.4 Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 12-2 on page 57, the PINxn Register bit and the pre-

ceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure 12-3

on page 59 shows a timing diagram of the synchronization when reading an externally applied

pin value. The maximum and minimum propagation delays are denoted t

pd,max

and t

pd,min

respectively.

Table 12-1. Port Pin Configurations

DDxn PORTxn

PUD

(in MCUCR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled low.

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)