Datasheet

54
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
• Bit 4– PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change inter-
rupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The
corresponding interrupt of pin change interrupt request is executed from the PCI0 interrupt
vector. PCINT7..0 pins are enabled individually by the PCMSK0 register.
11.2.3 GIFR – General Interrupt Flag Register
• Bits 7, 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes
set (logical one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will
jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT0 is configured as a level interrupt.
• Bit 5 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT11..8 pin triggers an interrupt request, PCIF1 becomes set
(logical one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump
to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 4– PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF becomes set
(logical one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump
to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
11.2.4 PCMSK1 – Pin Change Mask Register 1
• Bits 7, 4– Res: Reserved Bits
These bits are reserved bits in the Atmel
®
ATtiny24/44/84 and will always read as zero.
Bit 76543210
0x3A (0x5A – INTF0 PCIF1 PCIF0 – – – – GIFR
Read/Write RR/WR/WR/WRRRR
Initial Value00000000
Bit 7 6 5 4 3 2 1 0
0x20 (0x40) – – – – PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0