Datasheet

7701F–AVR–10/12

Atmel ATtiny24/44/84 [Preliminary]

11. External Interrupts

The external interrupts are triggered by the INT0 pin or any of the PCINT11..0 pins. Observe

that, if enabled, the interrupts will trigger even if the INT0 or PCINT11..0 pins are configured as

outputs. This feature provides a way of generating a software interrupt. Pin change 0 inter-

rupts (PCI0) will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts (PCI1)

will trigger if any enabled PCINT11..8 pin toggles. The PCMSK0 and PCMSK1 registers con-

trol which pins contribute to the pin change interrupts. Pin change interrupts on PCINT11..0

are detected asynchronously. This implies that these interrupts also can be used for waking

the part from sleep modes other than idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as

indicated in the specification for the MCU control register (MCUCR). When the INT0 interrupt

is enabled and is configured as level-triggered, the interrupt will trigger as long as the pin is

held low. Note that recognition of falling- or rising-edge interrupts on INT0 requires the pres-

ence of an I/O clock, described in “Clock Systems and their Distribution” on page 25. Low level

interrupt on INT0 is detected asynchronously. This implies that this interrupt also can be used

for waking the part from sleep modes other than idle mode. The I/O clock is halted in all sleep

modes except idle mode.

Note that if a level-triggered interrupt is used for wake-up from power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the start-up time, the MCU will still wake up, but no

interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses as

described in “System Clock and Clock Options” on page 25.

11.1 Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 11-1.

Figure 11-1. Timing of pin change interrupts

clk

PCINT(0)

pin_lat

pin_sync

pcint_in_(0)

pcint_syn

pcint_setflag

PCIF