Datasheet

7701F–AVR–10/12

Atmel ATtiny24/44/84 [Preliminary]

9.10 Register Description

9.10.1 MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU Reset.

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing

a logical zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing

a logical zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logical zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the

flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then

reset the MCUSR as early as possible in the program. If the register is cleared before another

reset occurs, the source of the reset can be found by examining the Reset Flags.

9.10.2 WDTCSR – Watchdog Timer Control and Status Register

• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con-

figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit

in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable

When this bit is written to logical one, WDE is cleared, and the I-bit in the status register is set,

the watchdog time-out interrupt is enabled. In this mode the corresponding interrupt is exe-

cuted instead of a reset if a time-out in the watchdog timer occurs.

Bit 76543210

0x34 (0x54) ––––WDRFBORFEXTRFPORFMCUSR

Read/Write RRRRR/WR/WR/WR/W

Initial Value0000 See Bit Description

Bit 7 6 5 4 3 2 1 0

0x21 (0x41) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X 0 0 0