Datasheet

41
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
Figure 9-1. Reset Logic
9.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection
level is defined in “System and Reset Characterizations” on page 181. The POR is activated
whenever V
CC
is below the detection level. The POR circuit can be used to trigger the Start-up
Reset, as well as to detect a failure in supply voltage.
A POR circuit ensures that the device is reset from power-on. Reaching the power-on reset
threshold voltage invokes the delay counter, which determines how long the device is kept in
RESET after V
CC
rise. The RESET signal is activated again, without any delay, when V
CC
decreases below the detection level.
Figure 9-2. MCU Start-up, RESET
Tied to V
CC
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [1..0]
Delay Counters
CKSEL[1:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
SUT
[
1:0
]
Power-on Reset
Circuit
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
RST
V
PORMAX
V
CC
CCRR
V
V
PORMIN