Datasheet

39
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
8.9.2 PRR – Power Reduction Register
• Bits 7, 6, 5, 4- Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 3- PRTIM1: Power Reduction Timer/Counter1
Writing a logical one to this bit shuts down the timer/counter 1 module. When the timer/counter
1 is enabled, operation will continue like before the shutdown.
• Bit 2- PRTIM0: Power Reduction Timer/Counter0
Writing a logical one to this bit shut s down the timer/counter 0 module. When the timer/coun-
ter 0 is enabled, operation will continue like before the shutdown.
• Bit 1 - PRUSI: Power Reduction USI
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When
waking up the USI again, the USI should be re initialized to ensure proper operation.
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut-
down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.
Bit 7 6 5 4 3 2 1 0
– – – – PRTIM1 PRTIM0 PRUSI PRADC PRR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0