Datasheet

32
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
7.10 Register Description
7.10.1 Oscillator Calibration Register – OSCCAL
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value
is automatically written to this register during chip reset, giving the Factory calibrated fre-
quency as specified in Table 22-2 on page 180. The application software can write this
register to change the oscillator frequency. The oscillator can be calibrated to frequencies as
specified in Table 22-2 on page 180. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to
more than 8.8MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to logical zero
gives the lowest frequency range, setting this bit to logical one gives the highest frequency
range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F
gives a higher frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in
the range.
7.10.2 Clock Prescaler Register – CLKPR
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logical one to enable change of the CLKPS bits. The CLK-
PCE bit is only updated when the other bits in CLKPR are simultaneously written to logical
zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are
written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out
period nor clear the CLKPCE bit.
• Bits 6..4 – Res: Reserved Bits
These bits are reserved bits in the Atmel
®
ATtiny24/44/84 and will always read as zero.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal sys-
tem clock. These bits can be written at run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the speed
of all synchronous peripherals is reduced when a division factor is used. The division factors
are given in Table 7-10 on page 33.
Bit 76543210
0x31 (0x51) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
Bit 76543210
0x26 (0x46)
CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R/W R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description