Datasheet

30
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
Figure 7-3. External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT Fuses as shown
in Table 7-8 on page 30.
When applying an external clock, sudden changes in the applied clock frequency must be
avoided to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in reset during such changes in the clock frequency.
Note that the system clock prescaler can be used to implement run-time changes of the inter-
nal clock frequency while still ensuring stable operation. See “System Clock Prescaler” on
page 31 for details.
Table 7-8. Start-up Times for the External Clock Selection
SUT1..0
Start-up Time from
Power-down and Power-save
Additional Delay from
Reset Recommended Usage
00 6CK 14CK BOD enabled
01 6CK 14CK + 4ms Fast rising power
10 6CK 14CK + 64ms Slowly rising power
11 Reserved
EXTERNAL
CLOCK
SIGNAL
CLKI
GND